Method of forming barrier metal in semiconductor device
View Patent ↗A method of forming a barrier metal in a semiconductor device. The present invention includes forming an insulating layer on a substrate having a lower metal line formed thereon, forming an opening exposing the lower metal line through the insulating layer, and forming a barrier metal layer on a sidewall of the opening and the insulating layer except the lower metal line by applying a positive voltage to the substrate.
1. A method of forming barrier metal in a semiconductor device, comprising the steps of: forming an insulating layer on a substrate having a lower metal line formed thereon; forming an opening exposing the lower metal line through the insulating layer; and forming a barrier metal layer on a sidewall of the opening and the insulating layer except the lower metal line by applying a positive voltage to the substrate.
2. The method of claim 1 , wherein the opening comprises a via hole and a trench.
3. The method of claim 1 , wherein the barrier metal layer is a single layer formed of Ta.
4. The method of claim 1 , wherein the barrier metal layer is a single layer formed of Ti.
5. The method of claim 1 , wherein the barrier metal layer is a double layer formed of Ti/TiN.
6. The method of claim 1 , wherein the barrier metal layer is a double layer formed of Ta/TiN.
7. The method of claim 1 , wherein the barrier metal layer is formed by ionized metal plasma physical vapor deposition.
8. The method of claim 1 , wherein the barrier metal layer is formed by collimator sputtering.
9. The method of claim 1 , wherein the barrier metal layer is formed by plasma enhanced metal organic chemical vapor deposition.
10. The method of claim 1 , wherein the positive voltage is applied to the substrate in a manner of applying the positive voltage to a wafer chuck having the substrate loaded thereon.
11. The method of claim 10 , wherein the voltage applied to the wafer chuck is about 1 to about 90 eV per unit area.
12. A method for forming barrier metal in a semiconductor device, comprising: a step for forming an insulating layer on a substrate having a lower metal line formed thereon; a step for forming an opening exposing the lower metal line through the insulating layer; and a step for forming a barrier metal layer on a sidewall of the opening and the insulating layer except the lower metal line by applying a positive voltage to the substrate.
13. The method of claim 12 , wherein the opening comprises a via hole and a trench.
14. The method of claim 12 , wherein the barrier metal layer is a single layer formed of Ta or Ti.
15. The method of claim 12 , wherein the barrier metal layer is a double layer formed of Ti/TiN or Ta/TiN.
16. The method of claim 12 , wherein the barrier metal layer is formed by ionized metal plasma physical vapor deposition.
17. The method of claim 12 , wherein the barrier metal layer is formed by collimator sputtering.
18. The method of claim 12 , wherein the barrier metal layer is formed by plasma enhanced metal organic chemical vapor deposition.
19. The method of claim 12 , wherein the positive voltage is applied to the substrate in a manner of applying the positive voltage to a wafer chuck having the substrate loaded thereon.
20. The method of claim 19 , wherein the voltage applied to the wafer chuck is about 1 to about 90 eV per unit area.