IP Library Granted Patent US 7,348,282
Granted Patent B2
US 7,348,282 · App. 11/024,849 · Granted Mar 25, 2008

Forming method of gate insulating layer and nitrogen density measuring method thereof

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Quick Facts
Patent No.
US 7,348,282
App. No.
11/024,849
Granted
Mar 25, 2008
Kind
B2
Abstract

A method of forming a gate insulating layer and nitrogen density measuring method thereof, by which a transistor having enhanced electric characteristics can be fabricated without employing separate ion implantation in a manner of providing parameters for enhancing perfection of the transistor via nitridation measurement. The method includes forming a first oxide layer on a silicon substrate having first to fourth regions defined thereon, patterning the first oxide layer in the first and fourth regions to have a predetermined thickness, and forming a nitride layer on the oxide layer in the third and fourth regions.

Claims (13)

1. A method of forming a gate insulating layer, comprising the steps of:

forming a first gate insulating oxide layer on a silicon substrate having first to fourth regions defined thereon;

patterning the first gate insulating oxide layer in the first and fourth regions so that the thickness of the first gate insulating oxide layer in the first and fourth regions becomes different from the thickness of the first gate insulating oxide layer in the second and third regions; and

forming an oxide-nitride layer on the first gate insulating oxide layer in the third and fourth regions after the patterning step.

2. The method of claim 1 , further comprising forming a second gate insulating oxide layer to cover the patterned first gate insulating oxide layer and the oxide-nitride layer.

3. The method of claim 1 , wherein the step of forming the oxide-nitride layer comprises a step of rapid thermal annealing.

4. The method of claim 1 , wherein the patterning step comprises patterning the first gate insulating oxide layer by wet etching.

5. The method of claim 4 , wherein the wet etching uses a HF etchant.

6. The method of claim 1 , wherein the step of forming the oxide-nitride layer comprises:

forming an oxide-nitride on the first gate insulating oxide layer in the first to fourth regions; and

removing the oxide-nitride layer from the first and second regions.

7. The method of claim 6 , wherein the step of removing the nitride layer comprises removing the nitride layer by wet etching.

8. The method of claim 7 , wherein the wet etching uses a H 3 PO 4 etchant.

Assignments (2)
CHANGE OF NAME Recorded May 23, 2006
From: DONGBU-ANAM SEMICONDUCTOR, INC.
To: DONGBU ELECTRONICS CO., LTD.
Reel/Frame 017663/0468 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 30, 2004
From: LEE, SANG YONG
To: DONGBUANAM SEMICONDUCTOR INC.
Reel/Frame 016139/0875 →