Methods of fabricating transistors in semiconductor devices
View Patent ↗A example disclosed semiconductor fabrication method includes forming a well region in a semconductor substrate where device isolation structures are formed, depositing a buffer oxide layer and a nitride layer on the semiconductor substrate, forming a dummy gate by patterning the nitride layer; depositing a liner oxide layer and an insulation layer on the buffer oxide layer and the dummy gate and performing a planarization process, removing the dummy gate and implanting ions, removing the liner oxide layer and the insulation layer and performing a thermal treatment, and forming a polysilicon gate electrode by using the buffer oxide layer as a gate oxide layer.
1. A fabricating method of a transistor in a semiconductor device comprising:
forming a well region in a semiconductor substrate where device isolation structures are formed;
depositing a buffer oxide layer and a nitride layer on the semiconductor substrate;
forming a dummy gate by patterning the nitride layer;
depositing a liner oxide layer and an insulation layer on the buffer oxide layer and the dummy gate and performing a planarization process;
removing the dummy gate and implanting ions;
removing the liner oxide layer and the insulation layer and performing a thermal treatment; and
forming a polysilicon gate electrode by using the buffer oxide layer as a gate oxide layer.
2. A method as defined by claim 1 , wherein the well region is formed by implanting ions into the semiconductor substrate.
3. A method as defined by claim 2 , wherein the well region is formed by performing a thermal treatment after the ions are implanted into the semiconductor substrate.
4. A method as defined by claim 1 , wherein the buffer oxide layer is formed with a thickness between about 30 Å and about 60 Å.
5. A method as defined by claim 1 , wherein the nitride layer comprises Si 3 N 4 with a thickness between about 500 Å and about 3000 Å.
6. A method as defined by claim 1 , wherein the liner oxide layer comprises LTO with a thickness between about 50 Å and about 100 Å.
7. A method as defined by claim 1 , wherein the insulation layer comprises BPSG with a thickness between about 2000 Å and about 3000 Å.
8. A method as defined by claim 1 , wherein the planarization process is performed through a CMP or an etch-back process.
9. A method as defined by claim 1 , wherein In+ions for an NMOS type and SB+ions for a PMOS type are implanted with an implantation energy between about 100 keV and about 500 keV and at a dose between about 1×10 12 and about 5×10 13 .
10. A method as defined by claim 1 , wherein N 2+ ions are additionally implanted with an implantation energy between about 10 keV and about 80 keV and at a dose between about 1×10 12 and about 1×10 13 .
11. A method as defined by claim 1 , wherein the thermal treatment is performed in an N 2 atmosphere at a temperature between about 800° C. and about 1000° C. for about 10 seconds to about 60 seconds.