Granted Patent B2

US 7,211,491 · App. 11/026,287 · Granted May 1, 2007

Abstract

Claims (13)

1. A method of fabricating a gate electrode of a semiconductor device comprising the steps of:

growing a silicon epitaxial layer on a silicon substrate;

making at least one trench through the epitaxial layer and filling the trench with a first oxide layer;

etching the first oxide layer to form reverse spacers in the trench;

depositing a second oxide layer and a polysilicon layer over the silicon substrate including the trench and the reverse spacers and removing some part of the second oxide layer and the polysilicon layer to form a gate;

implanting ions into the silicon substrate at both sides of the gate to form pocket-well and LDD areas;

depositing a nitride layer over the silicon substrate including the gate and etching the nitride layer to form spacers;

implanting ions using the spacers and the gate as a mask to make a source/drain region; and

forming a silicide layer on the top of the gate electrode and the silicon epitaxial layer positioned on the source/drain region.

2. The method as defined by claim 1 , wherein the reverse spacers are formed on the sidewalls of the trench by dry-etching and are a layer of TEOS or a multi-layer of TEOS—SiN—TEOS.

3. The method as defined by claim 1 , wherein the spacing between the reverse spacers defines the width of a gate channel.

4. The method as defined by claim 1 , wherein the step of implanting ions to form pocket-well and LDD areas forms shallow junction by using ions at a high energy level.

5. The method as defined by claim 1 , wherein the silicide layer formed on the silicon epitaxial layer which is positioned on the source/drain region functions as an elevated source/drain.

Assignments (8)