Method of fabricating semiconductor device employing selectivity poly deposition
View Patent ↗A method for fabricating a semiconductor device employing a selectivity poly deposition is disclosed. The disclosed method comprises depositing selectivity poly on a gate poly and source/drain regions of the silicon substrate, and forming salicide regions on the gate and active regions from the deposited selectivity poly. Accordingly, the present invention employing selectivity poly deposition can reduce or minimize contact surface resistance and improve the electrical characteristics of the semiconductor device by reducing the surface resistance in a miniature semiconductor device. In addition, because the size of the gate electrode is getting small, the present invention can be used as an essential part of the future generations of nano-scale technology. Moreover, mass semiconductor production systems can promptly employ the present invention with existing equipment.
1. A semiconductor device, comprising:
a) a gate poly structure, comprising a gate poly layer on a gate oxide on a silicon substrate;
b) source/drain regions on the silicon substrate;
c) a selectivity poly on the gate poly layer and the source/drain regions, the selectivity poly on the gate poly layer having a width greater than a gate poly width and the selectivity poly on the source/drain region having a width greater than a corresponding source/drain region width; and
d) salicide regions on the selectivity poly.
2. The semiconductor device as defined in claim 1 , wherein said salicide regions reduce a surface resistance of (i) a gate electrode comprising the gate poly layer and (ii) the source/drain regions.
3. The semiconductor device as defined in claim 1 , further comprising spacers on sidewalls of the gate poly layer.
4. The semiconductor device as defined in claim 3 , wherein the selectivity poly on the gate poly layer covers a portion of the spacers.
5. The semiconductor device as defined in claim 1 , further comprising a shallow trench isolation structure on, in or over the silicon substrate.
6. The semiconductor device as defined in claim 1 , wherein said gate poly layer has a width of about 0.13 μm or less.
7. The semiconductor device as defined in claim 1 , wherein the salicide regions comprise Ti/TiN or Co/Ti/TiN layers on the selectivity poly.
8. The semiconductor device as defined in claim 1 , wherein the source/drain regions each comprise a high concentration ion implantation region.
9. The semiconductor device as in claim 1 , further comprising lightly doped source/drain extension regions.
10. The semiconductor device as defined in claim 9 , wherein each of the lightly doped source/drain extension regions.
11. The semiconductor device as defined in claim 9 , wherein the lightly doped source/drain extension regions are in the substrate under the spacers.
12. The semiconductor device as defines in claim 1 , wherein the selectivity poly comprises silicon formed by selective epitaxial growth.
13. The semiconductor device as defined in claim 1 , wherein the selectivity poly on the gate poly layer covers a portion of the spacers.
14. The semiconductor device as defined in claim 1 , wherein the salicide comprises Ti/TiN on the selectivity.
15. The semiconductor device as defined in claim 1 , wherein the salicide comprises Co/Ti/TiN on the selectivity poly.
16. The semiconductor device as defined in claim 1 , further comprising a shallow trench isolation structure in the silicon substrate.
17. The semiconductor device as defined in claim 16 , wherein the selectivity poly is on the source/drain regions from the spacers to at least the shallow trench isolation structure.
18. The semiconductor device as defined in claim 17 , wherein the selectivity poly on one of the source/drain regions is also on a nearest portion of the shallow trench isolation structure.
19. The semiconductor device as defined in claim 1 , wherein the salicide comprises Ti silicide.
20. The semiconductor device as defined in claim 1 , wherein the salicide comprises Co silicide.