Granted Patent B2

US 7,338,858 · App. 11/026,715 · Granted Mar 4, 2008

Abstract

Claims (17)

1. A method of fabricating a nonvolatile memory, comprising:

sequentially forming a first insulating layer and a second insulating layer on a substrate where a predetermined device is formed;

forming a hard mask by etching the second insulation layer;

after forming the hard mask, depositing silicon on the substrate where the hard mask is formed, where in the silicon is formed conformally surrounding the hard mask;

forming quantum dots by etching the silicon through an etchback process, wherein the quantum dots are formed to a height less than the height of the hard mask;

removing the hard mask;

forming a third insulation layer on the substrate where the quantum dots are formed, and;

depositing a conductive layer on the third insulation layer and pattering it to form a gate.

2. The method as defined by claim 1 , wherein the first insulation layer is made of oxide.

3. The method as defined by claim 1 , wherein the second insulation layer is made of nitride.

4. The method as defined by claim 1 , wherein the second insulation layer is formed with a thickness between 100 Å and 500 Å.

5. The method as defined by claim 1 , wherein the silicon is deposited with a thickness between 10 Å and 200 Å.

6. The method as defined by claim 1 , wherein the third insulation layer is formed through a thermal oxidation process to cover the quantum dots.

7. The method as defined by claim 1 , wherein two quantum dots are positioned under the gate.

8. The method as defined by claim 1 , wherein one quantum dot is positioned under the gate.

9. The method as defined by claim 1 , wherein the first insulation layer and the third insulation layer are physically and chemically the same.

10. The method as defined by claim 1 , wherein the first insulation layer is formed through a thermal oxidation process.

Assignments (8)