Semiconductor interconnection line and method of forming the same
View Patent ↗An interconnection line of a semiconductor device and a method of forming the same using a dual damascene process are disclosed. An example interconnection line of a semiconductor device includes a semiconductor substrate, a first interconnection line formed on the substrate, an insulating layer pattern formed on the substrate to expose a portion of the first interconnection line, and a metal pad layer formed on the exposed portion of the first interconnection line. The example interconnection line also includes an intermediate insulating layer formed on the entire surface of the substrate and having a via hole and a trench exposing the metal pad layer, and a second interconnection formed in the via hole and the trench and electrically connected to the first interconnection line through the metal pad layer.
1. A method of forming an interconnection line for a semiconductor device, comprising:
providing a semiconductor substrate on which a first interconnection line is formed;
forming an insulating layer pattern exposing a portion of the first interconnection line on the substrate;
forming a metal pad layer on the exposed portion of the first interconnection line;
forming an intermediate insulating layer on the entire surface of the substrate;
etching the intermediate insulating layer to form a via hole exposing the metal pad layer;
etching a portion of the intermediate insulating layer to form a trench at an upper portion of the via hole; and
forming a second interconnection line electrically connected to the first interconnection line through the metal pad layer in the via hole and the trench.
2. The method of claim 1 , wherein forming the insulating layer pattern includes:
forming an insulating layer on the entire surface of the substrate;
forming a photoresist pattern exposing the portion of the insulating layer over the first interconnection line;
etching the insulating layer using the photoresist pattern; and
removing the photoresist pattern.
3. The method of claim 2 , wherein the insulating layer is formed of one selected from a silicon oxide (SiO 2 ) layer, an FSG (Fluoro-Silicate Glass) layer, and an insulating layer of a low dielectric constant (low-k) of below 3.0.
4. The method of claim 3 , wherein the intermediate insulating layer is formed of one selected from a silicon oxide (SiO 2 ) layer, an FSG (Fluoro-Silicate Glass) layer, and an insulating layer of a low dielectric constant (low-k) of below 3.0.
5. The method of claim 1 , wherein the metal pad layer is formed by a selective deposition method.
6. The method of claim 5 , wherein the metal pad layer is formed of one selected from a W layer, a Ti layer, a TiN layer, a Ta layer and a TaN layer.
7. The method of claim 1 , wherein the first and second interconnection lines are respectively formed of a Cu layer.
8. The method of claim 1 , wherein forming the second interconnection line includes:
forming a Cu layer on the intermediate insulating layer so as to fill the via hole and the trench; and
performing a planarization process so as to expose the intermediate insulating layer.
9. The method of claim 8 , wherein the planarization process is performed by chemical mechanical polishing (CMP).