Non-volatile memory device having upper and lower trenches and method for fabricating the same
View Patent ↗Non-volatile memory device, and method for fabricating the same are disclosed. By forming floating gate trenches in memory regions and filling the trenches with floating gate material, a step height of a with the floating gate/ONO/control gate structure is reduced to the level of a gate in a logic block, and the upper gate structures do not cause a topology imbalance. By forming a tunnel insulating film in the floating gate trenches, edges of the floating gate are in contact with the tunnel insulating film and included in an effective charge area of the device. By reducing the step height of the nonvolatile memory device and including edges of the floating gate in the effective charge area, the completed device can effectively perform its regular operations, such as erasure, programming, and reading.
1. A non-volatile memory device comprising:
an upper trench in a heavily doped region of a semiconductor substrate having a depth;
a lower trench in a bottom of the upper trench, in a lightly doped drain (LDDs) of the semiconductor substrate below the heavily doped region and in communication with the upper trench, wherein portions of corner surfaces of the upper trench remain;
a passivation pattern on the corner surfaces of the upper trench;
a tunnel insulating film on an inside surface of the lower trench;
a floating gate inside the upper and lower trenches and in contact with the tunnel insulating film and the passivation pattern;
a gate insulator layer on the floating gate; and
a control gate on the gate insulator layer.
2. The non-volatile memory device as claimed in claim 1 , wherein said heavily doped region comprises a source/drain diffusion layer on opposite sides of the upper trench.
3. The non-volatile memory device as claimed in claim 1 , wherein said LDDs are on opposite sides of the lower trench.
4. The non-volatile memory device as claimed in claim 1 , wherein the passivation pattern comprises a nitride spacer.
5. The non-volatile memory device as claimed in claim 1 , wherein the passivation pattern has a thickness of from about 200Å to about 500Å.
6. The non-volatile memory device as claimed in claim 2 , wherein said source/drain diffusion layer has a target depth about equal to the depth of the upper trench.
7. The non-volatile memory device as claimed in claim 6 , wherein the source/drain diffusion layer has a target depth of from about 500Å to about 2000Å.
8. The non-volatile memory device as claimed in claim 3 , wherein said LDDs have a target depth about equal to a depth of the lower trench.
9. The non-volatile memory device as claimed in claim 8 , wherein the LDD have a target depth of from about 1000Å to about 4000Å.
10. The non-volatile memory device as claimed in claim 1 , wherein the tunnel insulating film comprises a bottom portion along the bottom of the lower trench and sidewall portions along respective sidewalls of the lower trench.
11. The non-volatile memory device as claimed in claim 10 , wherein the sidewall portions of the tunnel insulating film have a greater thickness than the bottom portion of the tunnel insulating film.
12. The non-volatile memory device as claimed in claim 1 , wherein the tunnel insulating film comprises a thermally grown oxide.
13. The non-volatile memory device as claimed in claim 2 , wherein the tunnel insulating film and passivation pattern are configured to prevent exposure of the floating gate to the source/drain diffusion layer.
14. The non-volatile memory device as claimed in claim 2 , wherein the passivation pattern is configured to electrically insulate the source/drain diffusion layer from the floating gate.
15. The non-volatile memory device as claimed in claim 14 , wherein the passivation pattern has a surface in contact with the floating gate.
16. The non-volatile memory device as claimed in claim 1 , wherein the gate insulator layer comprises a silicon oxide layer.
17. The non-volatile memory device as claimed in claim 16 , wherein the gate insulator layer comprises an Oxide-Nitride-Oxide (ONO) pattern.
18. The non-volatile memory device as claimed in claim 1 , wherein the gate insulator layer contacts the passivation pattern.
19. The non-volatile memory device as claimed in claim 1 , wherein the floating gate substantially fills the upper and lower trenches.
20. The non-volatile memory device as claimed in claim 1 , wherein the floating gate comprises polysilicon.