Method for fabricating shallow trench isolation structure of semiconductor device
A method for fabricating a shallow trench isolation structure of semiconductor device is disclosed. The method for fabricating a shallow trench isolation structure of semiconductor device comprises growing a silicon oxide layer on a substrate, depositing a nitride layer with a predetermined thickness and growing a thermal oxide layer as a hard mask to dry-etch a substrate; forming a photoresist pattern through a photolithographic process and dry-etching the thermal oxide layer, the nitride layer and the silicon oxide layer to form a hard mask; removing the photoresist pattern through an ashing/strip process, depositing a layer for forming spacers as thick as critical dimension and pullback targets in order to compensate the regions made by a phosphoric acid strip process and etching the layer for forming spacers; forming silicon trenches using the spacers and the thermal oxide layer deposited on the spacers and the nitride layer; filling an oxide material into the substrate comprising the trenches to form field regions; performing a CMP process for planarizing the silicon nitride layer and the oxide material; and forming active regions and field regions by tuning the ratio of the height of the field region to that of the active region through an oxide layer wet etching process and a phosphoric acid strip process, and by removing the silicon nitride layer, the silicon oxide layer and the spacers.
1 . A method for fabricating a shallow trench isolation structure of semiconductor device comprising the steps of:
(a) growing a silicon oxide layer on a substrate, depositing a nitride layer with a predetermined thickness and growing a thermal oxide layer as a hard mask to dry-etch a substrate;
(b) forming a photoresist pattern through a photolithographic process and dry-etching the thermal oxide layer, the nitride layer and the silicon oxide layer to form a hard mask;
(c) removing the photoresist pattern through an ashing/strip process, depositing a layer for forming spacers as thick as critical dimension and pullback targets in order to compensate the regions made by a phosphoric acid strip process and etching the layer for forming spacers;
(d) forming silicon trenches using the spacers and the thermal oxide layer deposited on the spacers and the nitride layer;
(e) filling an oxide material into the substrate comprising the trenches to form field regions;
(f) performing a CMP process for planarizing the silicon nitride layer and the oxide material; and
(g) forming active regions and field regions by tuning the ratio of the height of the field region to that of the active region through an oxide layer wet etching process and a phosphoric acid strip process, and by removing the silicon nitride layer, the silicon oxide layer and the spacers.
2 . The method as defined by claim 1 , wherein the etching in the step (c) is dry etching.
3 . The method as defined by claim 1 , wherein the step (c) insures undercut regions by only depositing and etching the spacers.
4 . The method as defined by claim 1 , the spacers substitute the functions of a phosphoric acid strip process in order to insure the margin of critical dimension.