Method for forming copper wiring of semiconductor device

1 . A method for forming copper wiring, comprising:

forming a first copper wiring on a semiconductor substrate;

implanting magnesium ions into the first copper wiring;

thermally treating the first copper wiring to form a layer comprising magnesium oxide on the first copper wiring; and

forming a second copper wiring on the first copper wiring.

2 . The method of claim 1 , wherein forming the first copper wiring comprises:

depositing a first etch stop layer, an interlayer dielectric layer, a second etch stop layer, and a wiring dielectric layer on the semiconductor substrate;

etching the wiring dielectric layer, the second etch stop layer, and the interlayer dielectric layer to form a contact hole;

etching the wiring dielectric layer to form a trench;

depositing a barrier metal layer and metal thin layer on inner walls of the contact hole and the trench, and the underlying structure; and

removing the metal thin layer and the barrier metal layer from over the wiring dielectric layer by chemical mechanical polishing.

3 . The method of claim 2 , further comprising, after etching the wiring dielectric layer and before depositing the barrier metal layer and metal thin layer, etching the first etch stop layer to expose a surface of the substrate.

4 . The method of claim 2 , further comprising depositing a metal seed layer after depositing the barrier metal layer and before depositing the metal thin layer.

5 . The method of claim 1 , wherein the step of forming the second copper wiring includes:

depositing a second interlayer dielectric layer, a third etch stop layer, and a second wiring dielectric layer on the magnesium oxide-containing layer;

etching the second wiring dielectric layer, the third etch stop layer, and the second interlayer dielectric layer to form a second contact hole;

etching the second wiring dielectric layer to form a second trench;

depositing a second barrier metal layer and a second metal thin layer on inner walls of the second contact hole, the second trench, and the underlying structure; and

removing the second metal thin layer and the second barrier metal layer from over the second wiring dielectric layer by chemical mechanical polishing.

6 . The method of claim 5 , further comprising depositing a second metal seed layer after depositing the second barrier metal layer and before depositing the second metal thin layer.

7 . The method of claim 5 , further comprising, after etching the second wiring dielectric layer and before depositing the second barrier metal layer and second metal thin layer, etching the magnesium oxide-containing layer to expose a surface of the first copper wiring.

8 . The method of claim 1 , wherein the magnesium ions are implanted in a dose range of from about 1×10 14 to about 1×10 16 .

9 . The method of claim 1 , wherein the magnesium ions are implanted with an energy in the range of from 10 to about 50 keV.

10 . The method of claim 1 , wherein said thermally treating comprises heating the first copper wiring at a temperature in the range of from about 300 to 500° C.

11 . The method of claim 1 , wherein the magnesium oxide-containing layer has a thickness in the range of from about 300 to about 600 Å.

12 . A method for forming copper wiring, comprising:

forming a first copper wiring on a semiconductor substrate;

forming a magnesium-containing layer on the first copper wiring;

thermally treating the first copper wiring and the magnesium-containing layer to form a layer comprising magnesium oxide on the first copper wiring; and

forming a second copper wiring on the first copper wiring.

13 . The method of claim 12 , wherein forming the first copper wiring comprises:

depositing a first etch stop layer, a first interlayer dielectric layer, a second etch stop layer, and a first wiring dielectric layer on the semiconductor substrate;

etching the first wiring dielectric layer, the second etch stop layer, and the first interlayer dielectric layer to form a first contact hole;

etching the first wiring dielectric layer to form a first trench;

etching the first etch stop layer to expose a surface of the substrate;

depositing a first barrier metal layer, a first metal seed layer, and a first metal thin layer on inner walls of the first contact hole and the first trench, and on the exposed surface of the substrate; and

removing the first metal thin layer and the first barrier metal layer from over the first wiring dielectric layer by chemical mechanical polishing.

14 . The method of claim 12 , wherein the step of forming the second copper wiring includes:

depositing a second interlayer dielectric layer, a third etch stop layer, and a second wiring dielectric layer on the magnesium oxide-containing layer;

etching the second wiring dielectric layer, the third etch stop layer, and the second interlayer dielectric layer to form a second contact hole;

etching the second wiring dielectric layer to form a second trench;

etching the magnesium oxide-containing layer to expose a surface of the first copper wiring;

depositing a second barrier metal layer, a second metal seed layer, and a second metal thin layer on inner walls of the second contact hole, the second trench, and the exposed surface of the first copper wiring; and

removing the second metal thin layer and the second barrier metal layer from over the second wiring dielectric layer by chemical mechanical polishing.

15 . The method of claim 12 , wherein the magnesium ions are implanted in a dose range of from about 1×10 14 to about 1×10 16 .

16 . The method of claim 12 , wherein the magnesium ions are implanted with an energy in the range of from 10 to about 50 keV.

17 . The method of claim 12 , wherein said thermally treating comprises heating the first copper wiring at a temperature in the range of from about 300 to 500° C.

18 . The method of claim 12 , wherein the magnesium oxide-containing layer has a thickness in the range of from about 300 to about 600 Å.

19 . A semiconductor device having copper wiring thereon, comprising:

a semiconductor substrate;

a first etch stop layer, a first interlayer dielectric layer, and a first wiring dielectric layer on the semiconductor substrate, wherein the first etch stop layer and the first interlayer dielectric layer have a first contact hole therein, and the first wiring dielectric layer has a first trench therein;

a first barrier metal layer and a first metal thin layer in the first contact hole and the first trench, in contact with an exposed surface of the substrate;

a magnesium oxide-containing layer on the first metal thin layer and the first wiring dielectric layer;

a second interlayer dielectric layer and a second wiring dielectric layer on the magnesium oxide-containing layer, wherein the second interlayer dielectric layer and the magnesium oxide-containing layer have a second contact hole therein, and the second wiring dielectric layer has a second trench therein;

a second barrier metal layer and a second metal thin layer in the second contact hole and the second trench, in contact with an exposed surface of the first metal thin layer.

20 . The semiconductor device of claim 19 , further comprising a second etch stop layer between the first interlayer dielectric layer and the first wiring dielectric layer, and a third etch stop layer between the second interlayer dielectric layer and the second wiring dielectric layer,

21 . The semiconductor device of claim 19 , wherein the first and second metal thin layers each comprise copper.

22 . The semiconductor device of claim 19 , further comprising a first metal seed layer between the first barrier metal layer and the first metal thin layer and a second metal seed layer between the second barrier metal layer and the second metal thin layer.

23 . The semiconductor device of claim 22 , wherein the first and second metal thin layers and the first and second metal seed layers each comprise copper.