Method of fabricating a test pattern for junction leakage current
View Patent ↗A method of forming a salicide pattern for measuring junction leakage current is disclosed. An example method forms device isolation structures on a silicon substrate, forms a well region between the device isolation structures, forms source and drain regions on the well region, and forms a salicide layer on the source and drain regions. The example method also removes some part of the salicide layer, deposits an interlayer dielectric layer on the salicide layer, and forms via holes in the interlayer dielectric layer and filling metal into the via holes to form a via. The example method further planarizes the interlayer dielectric layer and the via, and forms metal interconnects on the interlayer dielectric layer.
1. A method of fabricating a test pattern for measuring a junction leakage current comprising:
forming device isolation structures on a silicon substrate;
forming a well region between the device isolation structures;
forming source and drain regions on the well region;
forming a salicide layer on the source and drain regions;
removing some part of the salicide layer;
depositing an interlayer dielectric layer on the salicide layer;
forming via holes in the interlayer dielectric layer and filling metal into the via holes to form a via;
planarizing the interlayer dielectric layer and the via; and
forming metal interconnects on the interlayer dielectric layer, wherein the salicide layer is selectively formed only in the via contact region of the via holes; whereby a test pattern for measuring a junction leakage current is fabricated.
2. A method as defined by claim 1 , wherein the source and drain regions are formed by implanting 31 P ions or 75 As ions for an N-type junction, or by implanting 11 B ions or BF 2 ions for a P-type junction.