IP Library Granted Patent US 7,256,122
Granted Patent B2
US 7,256,122 · App. 11/027,851 · Granted Aug 14, 2007

Method of fabricating semiconductor device

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Quick Facts
Patent No.
US 7,256,122
App. No.
11/027,851
Granted
Aug 14, 2007
Kind
B2
Abstract

The present invention provides a Cu line and method of forming the same, by which reliability (e.g., EM, BTS and the like) can be enhanced by replacing SiN by HfO x , which plays a role as a protective layer and/or an etch stop layer on a Cu line, prevents or inhibits galvanic corrosion due to Cu oxide, and inhibits or reduces additional formation of Cu oxide by gathering or scavenging oxygen atoms from —OH, O 2 , and H 2 O. The present method includes the steps of forming a trench in an insulating layer on a substrate, forming a planarized Cu layer in the trench, forming a HfO x layer on the planarized Cu layer, and thermally treating the substrate.

Claims (36)

1. A method of fabricating a semiconductor device, comprising the steps of:

forming a trench pattern in an insulating layer on a substrate;

forming a planarized Cu layer in the trench pattern;

depositing a protective layer comprising HfO 2 on the planarized Cu layer;

depositing a barrier layer on the protective layer; and thermally treating the substrate.

2. The method of claim 1 , wherein the barrier layer comprises silicon nitride.

3. The method of claim 1 , wherein forming the trench pattern comprises a damascene process.

4. A method of fabricating a semiconductor device, comprising the steps of:

forming a trench pattern in an insulating layer on a substrate;

forming a planarized Cu layer in the trench pattern;

depositing a protective layer comprising HfO 2 on the planarized Cu layer, and

annealing the substrate at a temperature of from about 200 to about 700° C.

5. The method of claim 4 , wherein the annealing is conducted in an atmosphere comprising oxygen, nitrogen and/or an inert noble gas.

6. The method of claim 5 , wherein the annealing comprises an atmosphere comprising oxygen.

7. The method of claim 4 , further comprising depositing a barrier layer on the protective layer.

8. The method of claim 7 , wherein the barrier layer comprises silicon nitride.

9. A method of fabricating a semiconductor device, comprising the steps of:

forming a trench pattern in an insulating layer on a substrate;

forming a planarized Cu layer in the trench pattern;

depositing a protective layer comprising HfO 2 on the planarized Cu layer by chemical vapor deposition; and

thermally treating the substrate.

10. The method of claim 9 , wherein the deposited HfO 2 has a thickness of from about 50 to about 2,000 Å.

11. The method of claim 3 , further comprising depositing a barrier layer on the protective layer.

12. The method of claim 9 , wherein the chemical vapor deposition comprises depositing the HfO 2 from a precursor selected from the group consisting of HfCl 4 , tetra(C 1 –C 4 -alkoxy)hafnium, and tetrakis(di-C 1 –C 4 -alkylamido)hafnium.

13. The method of claim 3 , wherein forming the trench pattern comprises depositing Cu in the trench and planarizing the deposited Cu.

14. The method of claim 12 , wherein the chemical vapor deposition comprises depositing the HfO 2 from a precursor selected from the group consisting of HfCl 4 and tetrakis(di-C 1 –C 4 -alkylamido)hafnium and an oxygen source selected from the group consisting of O 2 , O 3 , and N 2 O.

15. The method of claim 3 , wherein the chemical vapor deposition is conducted at a temperature of greater then 200° C.

16. The method of claim 9 , wherein the chemical vapor deposition is conducted at a temperature of less than 200° C., and the method further comprises annealing the protective layer at a temperature of from 200 to about 700° C.

17. The method of claim 16 , wherein the annealing is conducted in an atmosphere comprising oxygen, nitrogen and/or an inert noble gas.

18. A device, comprising:

an insulating layer on a substrate, the insulating layer having a trench therein;

a planar Cu layer in the trench;

a protective layer comprising HfO 2 on the Cu layer; and

a silicon nitride layer on the protective layer.

19. The device of claim 18 , wherein the protective layer has a thickness of from about 50 to about 2,000 Å.

20. The device of claim 18 , wherein the protective layer consists essentially of HfO 2 .

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 28, 2014
From: DONGBU HITEK CO., LTD.
To: DSS TECHNOLOGY MANAGEMENT, INC.
Reel/Frame 033035/0680 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR PREVIOUSLY RECORDED ON REEL 017654 FRAME 0078. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNOR SHOULD BE "DONGBUANAM SEMICONDUCTOR INC.". Recorded Jun 22, 2006
From: DONGBUANAM SEMICONDUCTOR INC.
To: DONGBU ELECTRONICS CO., LTD.
Reel/Frame 017829/0911 →
CHANGE OF NAME Recorded May 22, 2006
From: DONGANAM SEMICONDUCTOR INC.
To: DONGBU ELECTRONICS CO., LTD.
Reel/Frame 017654/0078 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 29, 2004
From: KIM, JUNG JOO
To: DONGBUANAM SEMICONDUCTOR INC.
Reel/Frame 016159/0986 →