Semiconductor memory device capable of stably setting mode register set and method therefor

1. A semiconductor memory device having a mode register set (MRS), comprising:

a decoding unit for decoding a plurality of address signals included in the MRS and outputting a plurality of decoded signals; and

an output unit for outputting a plurality of configuration signals and activating one of the plurality of configuration signals in response to the plurality of decoded signals, wherein the output unit keeps its previous output signals if more than one of the plurality of decoded signals are activated.

2. The semiconductor memory device as recited in claim 1 , wherein when the plurality of address signals are inputted as a reserved code of the MRS, more than one of the plurality of decoded signals are activated.

3. The semiconductor memory device as recited in claim 2 , wherein when one of the plurality of decoded signals is activated, a corresponding configuration signal is activated.

4. The semiconductor memory device as recited in claim 3 , wherein the output unit includes a plurality of RS-type latches each of which for receiving each of the plurality of decoded signals as reset signals and set signals.

5. The semiconductor memory device as recited in claim 4 , wherein each of the plurality of RS-type latches is cross coupled NAND gates.

6. The semiconductor memory device as recited in claim 5 , wherein the decoding unit includes:

a first inverter and a second inverter connected in series for receiving a first address signal;

a third inverter and a fourth inverter connected in series for receiving a second address signal;

a fifth inverter for receiving a third address signal;

a first NAND gate for receiving an output of the second inverter, and output of the fourth inverter and an output of the fifth inverter to output a first decoded signal; and

a second NAND gate for receiving an output of the first inverter, the output of the fourth inverter and the output of the fifth inverter to output a second decoded signal.

7. The semiconductor memory device as recited in claim 6 , wherein each RS-type latch includes:

a third NAND gate for receiving the first decoded signal and the second decoded signal to output a first configuration signal; and

a fourth NAND gate for receiving the first decoded signal and the second decoded signal to output a second configuration signal, wherein an output of the third NAND gate is inputted to the fourth NAND gate and an output of the fourth NAND gate is inputted to the third NAND gate.

8. A method for controlling a semiconductor memory device according to a mode register set (MRS), comprising the steps of:

a) decoding addresses inputted to the MRS;

b) determining whether or not the addresses inputted to the MRS are defined; and

c) activating a corresponding configuration signal if the addresses are defined or holding a previous configuration signal if the addresses are not defined.