Method and apparatus for increasing operating frequency of a system for testing electronic devices
View Patent ↗A test system includes a communications channel that terminals in a probe, which contacts an input terminal of an electronic device to be tested. A resistor is connected between the communications channel near the probe and ground. The resistor reduces the input resistance of the terminal and thereby reduces the rise and fall times of the input terminal. The channel may be terminated in a branch having multiple paths in which each path is terminated with a probe for contacting a terminal on electronic devices to be tested. Isolation resistors are included in the branches to prevent a fault at one input terminal from propagating to the other input terminals. A shunt resistor is provided in each branch, which reduces the input resistance of the terminal and thereby reduces the rise and fall times of the input terminal. The shunt resistor may also be sized to reduce, minimize, or eliminate signal reflections back up the channel.
1. An apparatus for interfacing test signals between a tester and an electronic device under test, said apparatus comprising:
a structure;
a plurality of channel terminals disposed on said structure and configured to connect electrically with communications channels from said tester;
a plurality of probes disposed on said structure and configured to contact test features of said electronic device;
a plurality of electrically conductive paths connecting ones of said channel terminals with ones of said probes; and
a plurality of shunt resistors disposed on said structure, each said shunt resistor directly connected to one of said conductive paths, wherein:
at least one of said conductive paths comprises a plurality of branches,
each said branch is electrically connected to one of said channel terminals,
each said branch terminates in a different one of said probes,
each said branch comprises an isolation resistor disposed within the branch between said channel terminal and said probe in which said branch terminates, and
each said branch is electrically connected from between said isolation resistor disposed within said branch and said probe in which said branch terminates, through one of said shunt resistors to a voltage potential.
2. The apparatus of claim 1 , wherein said shunt resistors are thin film resistors.
3. The apparatus of claim 1 , wherein said structure comprises a first substrate on which said probes are disposed.
4. The apparatus of claim 3 , wherein said shunt resistors are disposed on said first substrate.
5. The apparatus of claim 4 , wherein said shunt resistors are thin film resistors.
6. The apparatus of claim 4 , wherein said probes and said shunt resistors are disposed on a first surface of said first substrate.
7. The apparatus of claim 4 , wherein said shunt resistors are disposed within said first substrate.
8. The apparatus of claim 3 , wherein said structure further comprises a second substrate on which said channel terminals are disposed.
9. The apparatus of claim 1 , wherein said structure comprises a first substrate on which said probes are disposed.
10. The apparatus of claim 9 , wherein said shunt resistors are disposed on said first substrate.
11. The apparatus of claim 10 , wherein said isolation resistors are disposed on said first substrate.
12. The apparatus of claim 10 , wherein said probes and said shunt resistors are disposed on a first surface of said first substrate.
13. The apparatus of claim 10 , wherein said shunt resistors are thin film resistors and said isolation resistors are thin film resistors disposed on said first substrate.
14. The apparatus of claim 10 , wherein said shunt resistors are disposed within said first substrate.
15. The apparatus of claim 1 , wherein each said shunt resistor is connected to one of said conductive paths so as to reduce an input resistance of one of said test features of said electronic device.
16. The apparatus of claim 1 , wherein each said shunt resistor is connected from one of said conductive paths to ground.
17. The apparatus of claim 1 , wherein said communications channels are not disposed on said structure.
18. The apparatus of claim 1 , wherein said voltage potential is ground.
19. For use in a test system comprising a tester and a plurality of drive channels terminating in probes, a method of testing an electronic device comprising a plurality of input terminals comprising capacitance, said method comprising:
bringing said probes into contact with said input terminals;
utilizing switches to connect shunt resistors to ones of said drive channels, wherein said switches are configured selectively to connect and disconnect said shunt resistors from said ones of said drive channels;
providing test signals from said tester through said ones of said drive channels to said electronic device, wherein said test signals are alternating current signals;
utilizing said switches to disconnect said shunt resistors from said ones of said drive channels; and
providing second test signals through said drive channels while said shunt resistors are disconnected from said ones of said channels, said second test signals comprising direct current signals.
20. The method of claim 19 , wherein said shunt resistors are configured to increase a frequency at which said test signals can be provided from said tester through said ones of said drive channels to said electronic device.
21. The method of claim 19 , wherein said shunt resistors decrease rise times of said input terminals.
22. The method of claim 21 , wherein said shunt resistors decrease fall times of said input terminals.
23. The method of claim 19 , wherein while said shunt resistors are connected to said ones of said drive channels, each said shunt resistor provides a resistive electrical path between one of said drive channels and ground.
24. The method of claim 19 further comprising testing functional operation of said electronic device utilizing said test signals.