Overlay measurement target
View Patent ↗In an overlay metrology method used during semiconductor device fabrication, an overlay alignment mark facilitates alignment and/or measurement of alignment error of two layers on a semiconductor wafer structure, or different exposures on the same layer. A target is small enough to be positioned within the active area of a semiconductor device combined with appropriate measurement methods, which result in improved measurement accuracy.
1. An overlay error target mark, comprising:
a first mark portion formed within or on a first layer of an integrated circuit structure;
a second mark portion formed within or on a second layer of the integrated circuit structure;
wherein the first mark portion includes a substantially rectangle or square-shaped frame pattern and the second mark portion includes substantially a cross shaped pattern within the frame pattern of the first mark portion, the cross shaped pattern having four arms radiating from a central point of the cross shaped pattern; and
wherein the position of the first mark portion relative to the position of the second mark portion allows for measurement of overlay error between the first and second layers.
2. The mark of claim 1 wherein the first and second mark portions are printed by a microlithographic process.
3. The mark of claim 1 wherein the centers of the patterns are substantially coincident.
4. The mark of claim 1 where the horizontal and vertical dimensions of the mark are substantially the same.
5. The mark of claim 1 where the width of the frame formed by the first mark portion is at the design rule for the microlithographic process.
6. The mark of claim 1 wherein the rectangle or square-shaped frame pattern, or the cross shaped pattern, or both are formed by smaller pattern sub-elements.
7. The mark of claim 6 where at least one of the sub-elements is shaped substantially as circles, squares, or lines, or a combination of them.
8. The mark of claim 1 wherein the width of the lines in the cross formed by the second mark portion are at the design rule for the microlithographic process.
9. The mark of claim 1 , wherein there is a gap between the four arms at the central point of the cross shaped pattern.
10. The mark of claim 1 , wherein each of the arms has a width and a length, the length being greater than the width, wherein a first pair of arms are collinear along their lengths and a second pair of arms are collinear along their lengths and the first pair of arms and second pair of arms are orthogonal to each other.
11. A method for measuring overlay error in a semiconductor device, comprising the steps of:
placing a first mark portion in a first active device area on a first layer of the semiconductor device, with the first mark portion including a four-sided frame;
placing a second mark portion in a second active device area on a second layer of the semiconductor device, with the second mark portion including a cross having four arms radiating from a central point of the cross; and
measuring offset between the first mark portion and the second mark portion to determine the overlay error between the first layer and the second layer.
12. The method of claim 11 wherein the width of the frame and cross in the mark pattern are at or near the design rule of the microlithography process.
13. The method of claim 11 wherein either or both of the frame or cross are formed by sub-elements patterned at or near the design rule of the microlithography process.
14. The method of claim 11 , wherein there is a gap between the four arms at the central point of the cross.
15. The method of claim 11 , wherein each of the arms has a width and a length, the length being greater than the width, wherein a first pair of arms are collinear along their lengths and a second pair of arms are collinear along their lengths and the first pair of arms and second pair of arms are orthogonal to each other.
16. An overlay metrology mark formed within or on a semiconductor wafer, comprising:
a first mark portion formed within or on a first layer of an integrated circuit structure;
a second mark portion within or on a second layer of the integrated circuit structure;
wherein the first mark portion comprises a rectangle or square-shaped frame pattern;
wherein the second mark portion comprises four rectangles positioned in a cross shaped pattern contained within the frame pattern defined by the first mark portion, the four rectangles radiating from a central point of the cross shaped pattern; and
wherein a gap between the rectangles is sufficiently large enough to avoid substantial changes to the rectangular shape by the lithographic printing process.
17. The mark of claim 16 , wherein each of the rectangles has a width and a length, the length being greater than the width, wherein a first pair of rectangles are collinear along their lengths and a second pair of rectangles are collinear along their lengths and the first pair of rectangles and second pair of rectangles are orthogonal to each other.
18. A method for measuring overlay error in a semiconductor device, comprising:
placing a first mark portion in a first active device area on a first layer of the semiconductor device;
placing a second mark portion in a second active device area of a second layer of the semiconductor device;
wherein the first mark portion comprises a rectangle or square-shaped frame and the second mark portion comprising four rectangles positioned in a cross shape contained within the frame defined by the first mark potion, the four rectangles radiating from a central point of the cross shape;
wherein the largest dimension of the first or the second mark portion is less than 10 microns; and
measuring offset between the first mark portion and the second mark portion to determine the overlay error.
19. The method of claim 18 wherein there is a gap between the rectangles at the central point of the cross shape.
20. The method of claim 18 wherein the largest dimension of the first mark portion is 1 micron or less.
21. The method of claim 18 wherein the first and second mark portions are printed by a microlithography process.
22. The method of claim 19 wherein the rectangle-shaped frame pattern, or the cross shape pattern, or both are formed by smaller pattern sub-elements.
23. The method of claim 22 wherein at least one of the sub-elements is shaped substantially as circles, squares, or lines, or a combination of them.
24. The method of claim 18 , wherein each of the rectangles has a width and a length, the length being greater than the width, wherein a first pair of rectangles are collinear along their lengths and a second pair of rectangles are collinear along their lengths and the first pair of rectangles and second pair of rectangles are orthogonal to each other.
25. A method for measuring overlay error in a semiconductor device, comprising:
placing a first mark portion in a first active device area on a first layer of the semiconductor device;
placing a second mark portion in a second active device area of a second layer of the semiconductor device;
with the first and second mark portions forming a target 1 square micron or smaller;
optically imaging and measuring an offset between the first mark portion and the second mark portion to determine the overlay error.
26. The method of claim 25 , wherein the first mark portion comprises a rectangle or square-shaped frame and the second mark portion comprising four rectangles positioned in a cross shape contained within the frame defined by the first mark potion, wherein the four rectangles radiating from a central point of the cross shape; and wherein there is a gap between the rectangles at the central point of the cross shape.
27. The method of claim 26 , wherein each of the rectangles has a width and a length, the length being greater than the width, wherein a first pair of rectangles are collinear along their lengths and a second pair of rectangles are collinear along their lengths and the first pair of rectangles and second pair of rectangles are orthogonal to each other.