Nonvolatile memory device using hybrid switch cell
View Patent ↗A nonvolatile memory device using a hybrid switch cell comprises a plurality of hybrid switch cell arrays each having a hierarchical bit line structure including a main bit line and a sub bit line. In the nonvolatile memory device, each sub cell array having the hierarchical bit line structure including a main bit line and a sub bit line is provided as a cross point cell array that comprises a nonvolatile ferroelectric capacitor and a hybrid switch which does not require an additional gate control signal, thereby reducing the whole memory size.
1. A nonvolatile memory device using a hybrid switch cell, comprising:
a plurality of hybrid switch cell arrays each having a hierarchical bit line structure including a plurality of sub bit lines connected to one of a plurality of main bit lines, each hybrid switch cell array including a sub cell array having a plurality of unit hybrid switch cells arranged in row and column directions between a word line and a sub bit line, wherein a voltage of the sub bit line induced by cell data is converted into current so that a sensing voltage of a main bit line is induced;
a plurality of word line driving units for selectively driving the word lines of the plurality of hybrid switch cell arrays; and
a plurality of sense amplifiers for sensing and amplifying data applied from the plurality of hybrid switch cell arrays,
wherein each of the unit hybrid switch cells comprises a nonvolatile ferroelectric capacitor whose one terminal is connected to the word line, and a hybrid switch which is connected between the other terminal of the nonvolatile ferroelectric capacitor and the sub bit line and is selectively switched depending on a voltage applied to the word line and the sub bit lines,
wherein the hybrid switch comprises:
a PN diode switch connected in a forward direction between the other terminal of the nonvolatile ferroelectric capacitor and the sub bit line, and
a PNPN diode switch connected in a backward direction between the other terminal of the nonvolatile ferroelectric capacitor and the sub bit line.
2. The nonvolatile memory device according to claim 1 , further comprising:
a data bus shared by the plurality of sense amplifiers;
a main amplifier for amplifying data applied from the data bus;
a data buffer for buffering amplification data applied from the main amplifier; and
an input/output port for externally outputting output data applied from the data buffer and applying externally applied input data to the data buffer.
3. The nonvolatile memory device according to claim 1 , wherein each of the plurality of hybrid switch cell arrays comprises a plurality of sub cell arrays.
4. The nonvolatile memory device according to claim 3 , wherein each of the plurality of sub cell arrays comprises:
a plurality of unit hybrid switch cells each located where a plurality of word lines and a plurality of sub bit lines that are arranged in row and column directions cross each other;
a pull-up/pull-down driving switch for pulling up or pulling down the plurality of sub bit lines;
a first driving switch unit for controlling connection of the main bit line and the sub bit line; and
a second driving switch unit for pulling down the main bit line.
5. The nonvolatile memory device according to claim 1 , wherein the PN diode switch has a P-type region which is connected to the other terminal of the nonvolatile ferroelectric capacitor and a N-type region which is connected to the sub bit line.
6. The nonvolatile memory device according to claim 1 , wherein the PNPN diode switch has an upper N-type region which is connected to the other terminal of the nonvolatile ferroelectric capacitor and a lower P-type region which is connected to the sub bit line.
7. The nonvolatile memory device according to claim 1 , wherein when the voltage level of the word line is ‘high’, the hybrid switch is switched to turn on the PN diode switch so that data stored in the nonvolatile ferroelectric capacitor is read, and
when the voltage level of the word line is a negative voltage and the voltage level of the sub bit line is ‘high’, the hybrid switch is switched to turn on the PNPN diode switch so that a hidden data is written in the nonvolatile ferroelectric capacitor.
8. A nonvolatile memory device using a hybrid switch cell, comprising:
a plurality of hybrid switch cell arrays each having a hierarchical bit line structure including a plurality of sub bit lines connected to one of a plurality of main bit lines, each hybrid switch cell array including a sub cell array having a plurality of unit hybrid switch cells arranged in row and column directions between a word line and a sub bit line, wherein a voltage of the sub bit line induced by cell data is converted into current so that a sensing voltage of a main bit line is induced,
wherein the sub cell array comprises:
a unit hybrid switch cell including a nonvolatile ferroelectric capacitor whose one terminal is connected to the word line, and a hybrid switch which is connected between the other terminal of the nonvolatile ferroelectric capacitor and the sub bit line and is selectively switched depending on a voltage applied to the word line and the sub bit line;
a pull-up/pull-down driving switch for pulling up or pulling down the sub bit line;
a first driving switch unit for controlling connection between the main bit line and the sub bit line; and
a second driving switch unit for pulling down the main bit linen,
wherein the hybrid switch comprises:
a PN diode switch connected in a forward direction between the other terminal of the nonvolatile ferroelectric capacitor and the sub bit line, and
a PNPN diode switch connected in a backward direction between the other terminal of the nonvolatile ferroelectric capacitor and the sub bit line.
9. The nonvolatile memory device according to claim 8 , wherein the PN diode switch has a P-type region which is connected to the other terminal of the nonvolatile ferroelectric capacitor and a N-type region which is connected to the sub bit line.
10. The nonvolatile memory device according to claim 8 , wherein the PNPN diode switch has an upper N-type region which is connected to the other terminal of the nonvolatile ferroelectric capacitor and a lower P-type region which is connected to the sub bit line.
11. The nonvolatile memory device according to claim 8 , wherein when the voltage level of the word line is ‘high’, the hybrid switch is switched to turn on the PN diode switch so that data stored in the nonvolatile ferroelectric capacitor is read, and
when the voltage level of the word line is a negative voltage and the voltage level of the sub bit line is ‘high’, the hybrid switch is switched to turn on the PNPN diode switch so that a hidden data is written in the nonvolatile ferroelectric capacitor.