Device for electrostatic discharge protection and circuit thereof
View Patent ↗Disclosed herein are a device for electrostatic protection and circuit thereof. According to the present invention, a device for electrostatic discharge protection comprises first to third wells formed on a semiconductor substrate, a first device, which includes a well pick-up region, a source region and a double diffused drain region, which are formed in predetermined regions on the first well, and a gate formed in a predetermined region on the semiconductor substrate, a second device, which includes a source region, a double diffused drain region and a first active region, which are formed in predetermined regions on the second well, and a gate formed in a predetermined region on the semiconductor substrate, and a second active region formed on the third well, wherein the gate, the source region and the well pick-up region of the first device are connected to a ground pad; the drain of the first device, and the source and the gate of the second device are connected to a power source pad; and the drain and the first active region of the second device, and the second active region are connecter to an I/O pad. Therefore, a single ESD protection device can cope with ESD stress of six modes, which can occur in each of I/O cells. Accordingly, a layout area necessary for ESD protection can be reduced.
1. A circuit for electrostatic discharge protection, comprising:
an input buffer, which is connected between a power source pad and a ground pad and has one terminal connected to an I/O pad; and
a device for electrostatic discharge protection, which is connected between the power source pad, the ground pad and the I/O pad.
2. The circuit as claimed in claim 1 , wherein the device for electrostatic discharge protection comprises:
first to third wells formed on a semiconductor substrate;
a first device, which includes a well pick-up region, a source region and a double diffused drain region, which are formed in predetermined regions on the first well, and a gate formed in a predetermined region on the semiconductor substrate;
a second device, which includes a source region, a double diffused drain region and a first active region, which are formed in predetermined regions on the second well, and a gate formed in a predetermined region on the semiconductor substrate; and
a second active region formed on the third well,
wherein the gate, the source region and the well pick-up region of the first device are connected to a ground pad; the drain of the first device, and the source and the gate of the second device are connected to a power source pad; and the drain and the first active region of the second device, and the second active region are connecter to an I/O pad.
3. A circuit for electrostatic discharge protection, comprising:
an output buffer, which is connected between a power source pad and a ground pad and has one terminal connected to an I/O pad; and
a device for electrostatic discharge protection, which is connected between the power source pad, the ground pad and the I/O pad.
4. The circuit as claimed in claim 3 , wherein the device for electrostatic discharge protection comprises:
first to third wells formed on a semiconductor substrate;
a first device, which includes a well pick-up region, a source region and a double diffused drain region, which are formed in predetermined regions on the first well, and a gate formed in a predetermined region on the semiconductor substrate;
a second device, which includes a source region, a double diffused drain region and a first active region, which are formed in predetermined regions on the second well, and a gate formed in a predetermined region on the semiconductor substrate; and
a second active region formed on the third well,
wherein the gate, the source region and the well pick-up region of the first device are connected to a ground pad; the drain of the first device, and the source and the gate of the second device are connected to a power source pad; and the drain and the first active region of the second device, and the second active region are connecter to an I/O pad.
5. A circuit for electrostatic discharge protection, comprising:
an input buffer, which is connected between a power source pad and a ground pad and has one terminal connected to an I/O pad;
an output buffer, which is connected between a power source pad and a ground pad and has one terminal connected to an I/O pad; and
a device for electrostatic discharge protection, which is connected between the power source pad, the ground pad and the I/O pad.
6. The circuit as claimed in claim 5 , wherein the device for electrostatic discharge protection comprises:
first to third wells formed on a semiconductor substrate;
a first device, which includes a well pick-up region, a source region and a double diffused drain region, which are formed in predetermined regions on the first well, and a gate formed in a predetermined region on the semiconductor substrate;
a second device, which includes a source region, a double diffused drain region and a first active region, which are formed in predetermined regions on the second well, and a gate formed in a predetermined region on the semiconductor substrate; and
a second active region formed on the third well,
wherein the gate, the source region and the well pick-up region of the first device are connected to a ground pad; the drain of the first device, and the source and the gate of the second device are connected to a power source pad; and the drain and the first active region of the second device, and the second active region are connecter to an I/O pad.