Memory device and method for fabricating the same
View Patent ↗Disclosed are a memory device and a method for fabricating the same. The memory device includes: a substrate provided with a trench; a bit line contact junction formed beneath the trench; a plurality of storage node contact junctions formed outside the trench; and a plurality of gate structures each being formed on the substrate disposed between the bit line contact junction and one of the storage node contact junctions. Each sidewall of the trench becomes a part of the individual channels and thus, channel lengths of the transistors in the cell region become elongated. Accordingly, the storage node contact junctions have a decreased level of leakage currents, thereby increasing data retention time.
1. A memory device, comprising:
a substrate provided with a trench;
a bit line contact junction formed beneath the trench;
a plurality of storage node contact junctions formed outside the trench; and
a plurality of gate structures each being formed on the substrate disposed between the bit line contact junction and one of the storage node contact junctions.
2. The memory device of claim 1 , wherein the trench has sidewalls each being a part of a channel.
3. The memory device of claim 1 , wherein sidewalls of the trench are sloped by being narrowed down going towards a bottom portion of the trench.
4. The memory device of claim 1 , wherein sidewalls of the trench are formed to be perpendicular to a surface of the indented portion of the substrate.
5. The memory device of claim 1 , wherein the gate structures, the bit line contact junction and the storage node contact junctions are disposed such that portions of the substrate where the individual sidewalls of the trench are positioned are allocated in the center of respective channel regions.
6. The memory device of claim 1 , wherein each of the gate structures includes a first insulation layer, a polysilicon layer, a metal layer and a second insulation layer for use in a hard mask.
7. The memory device of claim 1 , wherein each of the gate structures includes a first insulation layer, a planarized polysilicon layer, a metal layer and a second insulation layer for use in a hard mask.
8. The memory device of claim 6 , wherein the first insulation layer and the second insulation layer are formed by using silicon oxide and silicon nitride, respectively.
9. The memory device of claim 7 , wherein the first insulation layer and the second insulation layer are formed by using silicon oxide and silicon nitride, respectively.
10. A memory device, comprising:
a substrate provided with a trench;
a first contact junction formed beneath the trench;
a plurality of second contact junctions formed outside the trench;
a plurality of gate structures each being formed on the substrate disposed between the first contact junction and one of the second contact junctions;
a first contact plug formed on the first contact junction by filling a space created between the gate structures; and
a plurality of second contact plugs formed on the second contact junctions by filling a space created between the gate structures.
11. The memory device of claim 10 , further including:
a bit line connected with the first contact junction through the first contact plug; and
a plurality of storage nodes connected with the second junctions through the second contact plugs, respectively.
12. The memory device of claim 10 , wherein the trench has sidewalls each being a part of a channel.
13. The memory device of claim 10 , wherein sidewalls of the trench are sloped by being narrowed down going towards a bottom portion of the trench.
14. The memory device of claim 10 , wherein sidewalls of the trench are formed to be perpendicular to a surface of the indented portion of the substrate.
15. The memory device of claim 10 , wherein the gate structures, the first contact junction and the second contact junctions are disposed such that portions of the substrate where the individual sidewalls of the trench are positioned are allocated in the center of respective channel regions.
16. The memory device of claim 10 , wherein each of the gate structures includes a first insulation layer, a polysilicon layer, a metal layer and a second insulation layer for use in a hard mask.
17. The memory device of claim 10 , wherein each of the gate structures includes a first insulation layer, a planarized polysilicon layer, a metal layer and a second insulation layer for use in a hard mask.
18. The memory device of claim 16 , wherein the first insulation layer and the second insulation layer are formed by using silicon oxide and silicon nitride, respectively.
19. The memory device of claim 17 , wherein the first insulation layer and the second insulation layer are formed by using silicon oxide and silicon nitride, respectively.
20. The memory device of claim 10 , further including a plurality of spacers formed on each sidewall of the gate structures.