Semiconductor-on-insulator silicon wafer
A method of fabricating a semiconductor-on-insulator semiconductor wafer is described that includes providing first and second semiconductor substrates. A first insulating layer is formed on the first substrate with a first predetermined stress and a second insulating layer is formed on the second substrate with a second predetermined stress different than the first predetermined stress. The first insulating layer is bonded to the second insulating layer to form a composite insulating layer bonding the first substrate to the second substrate and a portion of the one substrate is removed to form a thin crystalline active layer on the composite insulating layer. The first and second insulating layers are formed with different stresses to provide a desired composite stress, which can be any stress from compressive to unstressed to tensile, depending upon the desired application.
1. A method of fabricating a semiconductor-on-insulator semiconductor wafer comprising the steps of:
providing a first semiconductor substrate;
selecting a first material from a group consisting of SiO 2 , Si 3 N 4 , poly Si, and combinations thereof;
forming a first insulating layer of the first material on a surface of the first semiconductor substrate, forming the first insulating layer with a first predetermined stress;
providing a second semiconductor substrate;
selecting a second material from a group consisting of TiSi 2 , CoSi 2 , TaSi 2 , rare earth oxides, rare earth nitrides, rare earth phosphides, rare earth silicides, and combinations thereof;
forming a second layer of the second material on a surface of the second semiconductor substrate, forming the second layer with a second predetermined stress different than the first predetermined stress;
bonding the first insulating layer to the second layer to form a composite insulating layer bonding the first semiconductor substrate to the second semiconductor substrate; and
removing a portion of one of the first semiconductor substrate and the second semiconductor substrate to form a thin crystalline active layer on the composite insulating layer.
2. A method as claimed in claim 1 wherein the steps of selecting a first material and selecting a second material include selecting a method of formation of each of the first insulating layer and the second layer from the selected materials.
3. A method as claimed in claim 2 wherein the steps of selecting a method of formation for each of the first insulating layer and the second layer each include selecting a method of formation from a group of processes including thermal, CVD, TEOS, plasma, sputtered, LPCVD, and commercial CMOS.
4. A method as claimed in claim 2 wherein the steps of forming the first insulating layer with the first predetermined stress and forming the second layer with the second predetermined stress each include selecting a layer thickness that provides the predetermined stress.
5. A method as claimed in claim 1 wherein the step of providing the second semiconductor substrate includes providing a crystalline germanium substrate.
6. A method as claimed in claim 5 wherein the step of removing a portion of one of the first semiconductor substrate and the second semiconductor substrate includes removing a portion of the crystalline germanium substrate to form a thin crystalline active germanium layer.
7. A method of fabricating a semiconductor-on-insulator semiconductor wafer comprising the steps of:
providing a first silicon substrate;
forming a layer including a first material selected from a group consisting of SiO 2 , Si 3 N 4 , poly Si, and combinations thereof on a surface of the first silicon substrate, forming the layer of first material with a first predetermined stress;
providing a second silicon substrate;
forming a layer including a second material selected from a group consisting of TiSi 2 , CoSi 2 , TaSi 2 , rare earth oxides, rare earth nitrides, rare earth phosphides, rare earth silicides, and combinations thereof on a surface of the second silicon substrate, and forming the layer of second material with a second predetermined stress different than the first predetermined stress;
bonding the layer of first material to the layer of second material using Van der Waal's bonding to form a composite insulating layer bonding the first silicon substrate to the second silicon substrate; and
removing a portion of the second silicon substrate to form a thin crystalline active layer on the composite insulating layer.
8. A method as claimed in claim 7 wherein the steps of providing the first silicon substrate and providing the second silicon substrate include providing a high quality silicon substrate for the second silicon substrate and providing a lower quality silicon substrate for the first silicon substrate.
9. A method as claimed in claim 7 wherein the steps of forming a layer of first material and forming a layer of second material each include selecting a method of formation of the layer of first material and the layer of second material from a group of processes including thermal, CVD, TEOS, plasma, sputtered, LPCVD, and commercial CMOS.
10. A method as claimed in claim 7 wherein the steps of forming the layer of first material with the first predetermined stress and forming the layer of second material with the second predetermined stress each include selecting a layer thickness that provides the predetermined stress.
11. A method as claimed in claim 7 wherein the steps of forming the layer of first material with the first predetermined stress includes forming the layer of first material with a compressive stress and forming the layer of second material with the second predetermined stress includes forming the layer of second material with a tensile stress substantially equal to the compressive stress.