IP Library Granted Patent US 7,310,239
Granted Patent B1
US 7,310,239 · App. 11/062,112 · Granted Dec 18, 2007

IC packaging interposer having controlled impedance or optical interconnections and an integral heat spreader

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Quick Facts
Patent No.
US 7,310,239
App. No.
11/062,112
Granted
Dec 18, 2007
Kind
B1
Abstract

Disclosed are embodiments of an integrated circuit die interconnection interposer suited to controlled high performance transmission of electronic or optical signals or combinations thereof. The various embodiments are designed to provide direct path interconnections away from the surface of one or more integrated circuit die. The structures are amenable to improved thermal management and can be fabricated on at semiconductor wafer.

Claims (24)

1. An electrical interconnect structure for interconnecting with at least one integrated circuit die, the electrical interconnect structure comprising:

a conductive core having first and second sides, the first side including first and second surfaces arranged in a stairstep relationship to each other, wherein the first surface is a conductive surface;

a first aperture extending through the conductive core from the first surface to the second side, the first aperture having a conductive circumferential wall;

a second aperture extending through the conductive core from the second surface to the second side;

a first signal path extending through the first aperture and having an end adapted to connect to an integrated circuit device, wherein the first signal path is electrically conductive;

a second signal path extending through the second aperture, and;

a first insulating member disposed within the first aperture to electrically insulate the first signal path from the conductive circumferential wall of the first aperture.

2. The electrical interconnect structure of claim 1 further comprising a circuit layer, at least a portion of the circuit layer being conductively coupled to the first signal path.

3. The electrical interconnect structure of claim 1 further comprising at least one optical connection path that extends through the electrical interconnect structure.

4. The electrical interconnect structure of claim 1 wherein the second aperture has a conductive circumferential wall, and wherein the second signal path is a conductive signal path, the electrical interconnect structure further comprising a second insulating member disposed within the second aperture to electrically insulate the second signal path from the conductive circumferential wall of the second the aperture.

5. The electrical interconnect structure claim 1 wherein the first signal path is substantially centered within the first insulating member such that the conductor and the wall of the conductive core form a coaxial signal path.

6. The electrical interconnect structure of claim 5 wherein the coaxial signal path has a controlled impedance.

7. The electrical interconnect structure of claim 1 further comprising a resistive device coupled to the first signal path.

8. The electrical interconnect structure of claim 7 wherein the resistive device is formed integrally with the electrical interconnect structure.

9. The electrical interconnect structure of claim 1 further comprising a capacitive device coupled to the first signal path.

10. The electrical interconnect structure of claim 9 wherein the capacitive device is formed integrally with the electrical interconnect structure.

11. The electrical interconnect structure of claim 1 further comprising an electro-static discharge (ESD) protection element coupled to the first signal path.

12. The electrical interconnect structure of claim 11 wherein the ESD protection element is formed integrally with the electrical interconnect structure.

13. The electrical interconnect structure of claim 1 wherein the conductive core comprises an insulating substrate plated with conductive material.

14. The electrical interconnect structure of claim 1 wherein the conductive core forms a ground element.

15. The electrical interconnect structure of claim 1 further comprising:

a layer of circuit traces wherein the circuit traces are interconnected to a plurality of conductive signal paths extending thorough a respective plurality of apertures in the conductive core conductor, each of the plurality of apertures having a conductive circumferential wall, including the first signal path extending through the first aperture; and

a plurality of insulating members, each insulating member disposed within a corresponding one of the plurality of apertures to isolate the each of the conductive signal paths from the conductive circumferential wall of its respective aperture.

16. The electrical interconnect structure of claim 1 wherein the conductive core is comprised of an electrically conductive material.

Assignments (7)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 7, 2010
From: TECHNOLOGY PROPERTIES LIMITED
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 025105/0596 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 7, 2010
From: INTERCONNECT PORTFOLIO, LLC; INTELLASYS BEC LIMITED; TECHNOLOGY PROPERTIES LIMITED
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 025105/0634 →
LICENSE Recorded Mar 4, 2009
From: INTERCONNECT PORTFOLIO LLC
To: TECHNOLOGY PROPERTIES LIMITED LLC
Reel/Frame 022343/0351 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 18, 2008
From: NOVIAS, LLC
To: INTERCONNECT PORTFOLIO, LLC
Reel/Frame 021861/0111 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 23, 2008
From: ANDERSON, DAN; FJELSTAD, JOE; GRUNDY, KEVIN; GRUNDY, LAWRENCE; STEPOVICH, MATT
To: NOVIAS, LLC
Reel/Frame 021731/0712 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 7, 2008
From: SILICON PIPE, INC.
To: SECURE NOTE HOLDERS: DAN ANDERSON, JOSEPH FJELSTAD, KEVIN GRUNDY, LAURANCE GRUNDY, MATT STEPOVICH
Reel/Frame 021380/0249 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 23, 2005
From: FJELSTAD, JOSEPH C.; GRUNDY, KEVIN P.
To: SILICON PIPE, INC.
Reel/Frame 016268/0036 →