IP Library Granted Patent US 7,362,079
Granted Patent B1
US 7,362,079 · App. 11/068,419 · Granted Apr 22, 2008

Voltage regulator circuit

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Quick Facts
Patent No.
US 7,362,079
App. No.
11/068,419
Granted
Apr 22, 2008
Kind
B1
Abstract

A voltage regulator circuit has a standby amplifier with an output coupled to a gate of an output transistor. An active amplifier has an output coupled to the gate of the output transistor and to a gate of a replica follower transistor. A voltage regulated output is coupled to a source of the output transistor.

Claims (28)

1. A voltage regulator circuit, comprising:

a standby amplifier having an output coupled to a gate of an output transistor;

an active amplifier having an output coupled to the gate of the output transistor and to a gate of a replica follower transistor; and

a voltage regulated output coupled to a source of the output transistor.

2. The circuit of claim 1 , further including a chip enable signal coupled to the gate of the output amplifier.

3. The circuit of claim 2 , further including a capacitor between the chip enable signal and the gate of the output transistor.

4. The circuit of claim 1 , wherein the replica follower transistor is significantly smaller than the output transistor.

5. The circuit of claim 1 , wherein the active amplifier is an open loop control amplifier.

6. The circuit of claim 5 , wherein a positive input of the active amplifier is coupled to a reference voltage and a negative input is coupled to a replica follower circuit.

7. The circuit of claim 6 , wherein a positive input of the standby amplifier is coupled to the reference voltage and a negative input coupled to a output circuit.

8. A voltage regulator circuit, comprising:

a closed loop amplifier having an output coupled to a gate of an output transistor;

an open control amplifier having an output coupled to the gate of the output transistor and a gate of a replica follower transistor; and

a voltage regulated output coupled to a source of the output transistor.

9. The circuit of claim 8 , wherein an external voltage is coupled to a drain of the output transistor and a pair of resistors is coupled in series between the source of the output transistor and a ground.

10. The circuit of claim 9 , further including a chip enable signal coupled to the gate of the output transistor.

11. The circuit of claim 10 , further including a capacitor coupled between the chip enable signal and the gate of the output transistor.

12. The circuit of claim 8 , wherein an external voltage is coupled to a drain of the replica follower transistor and a pair of resistors is coupled in series between the source of the replica follower transistor and a ground.

13. The circuit of claim 12 , wherein a negative input of the open control amplifier is coupled to a node between the pair of resistors.

14. The circuit of claim 13 , wherein a positive input of the open control amplifier is coupled to a reference voltage.

15. A voltage regulator circuit comprising:

an amplifier having an output coupled to a gate of an output transistor;

a chip enable signal directly electrically connected to a capacitor, the capacitor directly electrically connected to the gate of the output transistor; and

a voltage regulated output coupled to a source of the output transistor.

16. The circuit of claim 15 , wherein the amplifier includes a standby amplifier and an active amplifier, wherein an output of the active amplifier is coupled to the gate of a replica follower transistor and the gate of the output transistor.

17. The circuit of claim 16 , wherein the output transistor is larger than the replica follower transistor.

18. The circuit of claim 15 , further including a reference voltage coupled to an input of the amplifier.

19. The circuit of claim 18 , wherein a second input of the amplifier is coupled to a node between a pair of resistors coupled between a source of the output transistor and a ground.

Assignments (4)
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
RELEASE OF SECURITY INTEREST Recorded Jun 12, 2017
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 042769/0227 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 29, 2017
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MONTEREY RESEARCH, LLC
Reel/Frame 042108/0880 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →