SONOS memory cells and arrays and method of forming the same
View Patent ↗A trench ( 2 ) is fabricated in a silicon body ( 1 ). The walls ( 4 ) of the trench are provided with a nitrogen implantation ( 6 ). An oxide layer between the source/drain regions ( 5 ) and a word line applied on the top side grows to a greater thickness than a lower oxide layer of an ONO storage layer fabricated as gate dielectric at the trench wall. Instead of the nitrogen implantation into the trench walls, it is possible to fabricate a metal silicide layer on the top sides of the source/drain regions in order to accelerate the oxide growth there.
1. A method for fabricating memory cells, the method comprising:
etching a trench having a bottom and lateral walls at a top side of a silicon region;
introducing dopant for forming source and drain regions into the top side of the silicon region, the source and drain regions being adjacent to a top side of the trench and at the bottom of the trench;
covering the top side of the silicon region which adjoins the trench and the bottom of the trench with a resist mask;
implanting nitrogen into the lateral walls of the trench;
removing the resist mask;
forming a metal silicide layer in those regions of a top side of the silicon region which adjoin the trench and at the bottom of the trench;
simultaneously forming a gate dielectric at the lateral walls of the trench and an oxide layer at the top sides of said source and drain regions over the metal silicide layer; and
forming a gate electrode in the trench, the gate dielectric arranged between the gate electrode and the lateral walls of the trench.
2. The method according to claim 1 , wherein the metal silicide layer is fabricated as a CoSi 2 layer.
3. The method according to claim 2 , wherein forming the metal silicide layer comprises performing a salicide process.
4. The method according to claim 1 , wherein the gate dielectric comprises a lower boundary layer of a storage layer, the method further comprising:
forming the storage layer over the lower boundary layer; and
forming an upper boundary layer over the storage layer.
5. The method according to claim 4 , wherein the upper and lower boundary layers comprise oxide layers and wherein the storage layer comprises a nitride layer.
6. The method according to claim 1 , wherein the silicon region comprises a silicon layer.
7. The method according to claim 1 , wherein the silicon region comprises a silicon substrate.
8. The method according to claim 1 , further comprising forming a word line that is electrically coupled to the gate electrode.
9. A method for fabricating a memory cell, the method comprising:
etching a trench having a bottom and lateral walls at a top side of a silicon region;
introducing dopants for forming source and drain regions into the silicon region in an area adjoining the trench and at the bottom of the trench;
forming spacers at the lateral walls of the trench;
forming a metal silicide layer in those regions of the top side of the silicon region that adjoin the trench and at the bottom of the trench;
providing an electrically insulating layer at top sides of the source and drain regions, the electrically insulating layer overlying the metal silicide layer;
removing the spacers;
forming a gate dielectric layer at the lateral walls of the trench and simultaneously reinforcing the electrically insulating layer at the top side of the source and drain regions; and
forming a gate electrode in the trench, the gate dielectric layer being arranged between the gate electrode and the lateral walls of the trench.
10. The method according to claim 9 , wherein the metal silicide layer comprises a CoSi 2 layer.
11. The method according to claim 10 , wherein forming the metal silicide layer comprises performing a salicide process.
12. The method according to claim 9 , wherein forming a gate dielectric layer comprises forming a lower boundary layer, the method further comprising:
forming a storage layer over the lower boundary layer; and
forming an upper boundary layer over the storage layer.
13. The method according to claim 12 , wherein the lower boundary layer and the electrically insulating layer comprise oxide layers.
14. The method according to claim 13 , wherein the storage layer comprises a nitride layer and the upper boundary layer comprises an oxide layer.
15. The method according to claim 9 , further comprising forming a thermal oxide at the lateral walls of the trench prior to forming the spacers at the lateral walls of the trench.
16. The method according to claim 9 , further comprising forming a word line that is electrically coupled to the gate electrode.
17. A method for fabricating a memory cell, the method comprising:
etching a trench having a bottom and lateral walls at a top side of a silicon region;
introducing dopants for forming source and drain regions into the silicon region in an area adjoining the trench and at the bottom of the trench;
forming an oxide layer at the lateral walls of the trench;
forming spacers at the lateral walls of the trench overlying the oxide layer;
performing a salicide process to form a metal silicide layer in those regions of the top side of the silicon region that adjoin the trench and at the bottom of the trench;
providing an electrically insulating layer at top sides of the source and drain regions, the electrically insulating layer overlying the metal silicide layer;
removing the spacers to uncover the oxide layer, the oxide layer serving as a lower boundary layer;
forming a storage layer over the lower boundary layer;
forming an upper boundary layer over the storage layer;
forming a gate electrode in the trench; and
forming a word line that is electrically coupled to the gate electrode.
18. The method according to claim 17 , wherein the metal silicide layer comprises a CoSi 2 layer.
19. The method according to claim 17 , wherein the upper and lower boundary layers comprise oxide layers and wherein the storage layer comprises a nitride layer.
20. The method according to claim 19 , wherein providing the electrically insulating layer comprises forming an oxide layer.