Package configuration and manufacturing method enabling the addition of decoupling capacitors to standard package designs
View Patent ↗The present invention is directed to a method of fabricating an integrated circuit package having decoupling capacitors using a package design conceived for use without decoupling capacitors. The package is implemented with a minimal redesign of the original design and not requiring any redesign of the signal trace pattern. The invention involves replacing top and bottom bond pads with via straps and then covering the top and bottom reference planes with a dielectric layer having conductive vias that electrically connect with the underlying via straps. Planes having the opposite polarity of the underlying reference plane are then formed on the dielectric layer. These planes include an array of bonding pads in registry with the vias. Decoupling capacitors are mounted to the top of the package and electrically connected with the plane on top of the package and the immediately underlying reference plane without the electrical connections to the capacitors passing through the signal planes of the package.
1. An integrated circuit package comprising:
a multi-layer package substrate configured for use without decoupling capacitors and arranged in a stripline configuration with a plurality of striplines, each stripline having at least one signal plane positioned between an associated pair of reference planes, the multi-layer package having an upper package surface and a lower package surface configured so that the upper package surface has a first plane formed thereon wherein the first plane comprises a reference plane of a first stripline and the lower package surface having a second plane formed thereon wherein the second plane comprises one of a reference plane of a second stripline;
a first dielectric layer formed over the upper package surface and first plane;
a second dielectric layer formed over the lower package surface and second plane;
a first supplemental plane formed on a top surface of the first dielectric layer, the first supplemental plane having a polarity opposite of the first plane, the first supplemental plane being configured to include a decoupling capacitor;
a second supplemental plane formed on a bottom surface of the second dielectric layer, the second supplemental plane having a polarity opposite of the second plane; and
at least one decoupling capacitive element.
2. An integrated circuit package as in claim 1 wherein the at least one decoupling capacitive element includes a discrete capacitor mounted to the first supplemental plane.
3. An integrated circuit package as in claim 2 wherein:
the first plane comprises a ground plane of the first stripline
wherein the second plane comprises a power plane of the second stripline;
wherein the first supplemental plane comprises a power plane; and
wherein the second supplemental plane comprises a ground plane.
4. An integrated circuit package as in claim 3 wherein:
the first supplemental plane comprises an array of bond pads for connecting with an integrated circuit die; and
wherein the second supplemental plane comprises an array of bond pads configured for solder ball attachment.
5. An integrated circuit package as in claim 1 wherein the first dielectric layer comprises the at least one decoupling capacitive element and wherein the first dielectric layer comprises a layer of high-K dielectric material.
6. An integrated circuit package as in claim 1 wherein the first dielectric layer comprises the at least one decoupling capacitive element and wherein the first dielectric layer comprises a layer of low-K dielectric material.
7. An integrated circuit package as in claim 1 wherein the striplines each include a plurality of signal layers.
8. The integrated circuit package of claim 1 wherein the first plane includes via straps formed on the upper package layer surface, the via straps are electrically connected with the at least one signal plane of the first stripline by at least one conductive via that passes through a portion of the multi-layer package substrate to connect with the at least one signal plane of the first stripline;
wherein the first supplemental plane includes bond pads that are electrically connected with the via straps of the first plane by conductive vias that pass through the first dielectric layer to connect the bond pads with the via straps;
wherein the second plane includes via straps formed on the lower package layer surface, the via straps are electrically connected with the at least one signal plane of the second stripline by at least one conductive via that passes through a portion of the multi-layer package substrate to connect with the at least one signal plane of the second stripline; and
wherein the second supplemental plane includes bond pads that are electrically connected with the via straps of the second plane by conductive vias that pass through the second dielectric layer to connect the bond pads with the via straps.
9. An integrated circuit package as recited in claim 1 wherein said decoupling capacitor of the first supplemental plane includes electrical connections that electrically connect the capacitor to the first plane and to the first supplemental plane in a manner such that the electrical connections do not pass through the signal planes of the substrate.