IP Library › Assignment 050635/0001

Patent Assignment

Reel/Frame 050635/0001

Assignment of Assignor's Interest

Recorded: 2019-10-04 Pages: 104

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Assignors

AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.

Executed: 2017-12-08

BROADCOM CORPORATION

Executed: 2017-12-08

Assignee

BELL SEMICONDUCTOR, LLC

401 N. MICHIGAN AVE., SUITE 1600, CHICAGO, ILLINOIS, 60611

Covered Properties (30)

Method for Mounting a Microelectronic Circuit Peripherally-Leaded Package Including Integral Support Member with Spacer

Patent: 5,673,479 →

Application: 08/323,817 →

A Method of Planarizing an Array of Plastically Deformable Electrical Contacts on an Integrated Circuit Package to Compensate for Bottom Surface Warpage

Patent: 5,745,986 →

Application: 08/506,382 →

Microelectronic Integrated Circuit Mounted on Circuit Board with Solder Column Grid Array Interconnection, and Method of Fabricating the Solder Column Grid Array

Patent: 5,639,696 →

Application: 08/595,022 →

Apparatus to Decouple Core Circuits Power Supply from Input-Output Circuits Power Supply in a Semiconductor Device Package

Patent: 5,672,911 →

Application: 08/655,599 →

Ball Grid Array Package with Inexpensive Threaded Secure Locking Mechanism to Allow Removal of a Threaded Heat Sink Therefrom

Patent: 5,789,813 →

Application: 08/724,076 →

Ball Grid Array with Inexpensive Threaded Secure Locking Mechanism to Allow Removal of a Threaded Heat Sink Therefrom

Patent: 5,885,848 →

Application: 08/901,489 →

System and Method for Empirically Determining Shrinkage Stresses in a Molded Package and Power Module Employing the Same

Patent: 5,925,827 →

Application: 08/938,619 →

Semiconductor Device and Fabrication Method Which Advantageously Combine Wire Bonding and Tab Techniques to Increase Integrated Circuit I/O Pad Density

Patent: 5,973,397 →

Application: 08/955,929 →

Removal of a Heat Spreader from an Integrated Circuit Package to Permit Testing of the Integrated Circuit and Other Elements of the Package

Patent: 6,117,352 →

Application: 08/975,025 →

Semiconductor Device Package Including a Substrate Having Bonding Fingers Within an Electrically Conductive Ring Surrounding a Die Area and a Combined Power and Ground Plane to Stabilize Signal Path Impedances

Patent: 6,064,113 →

Application: 09/006,356 →

Device and Method of Manufacture for an Integrated Circuit Having a Bist Circuit and Bond Pads Incorporated Therein

Patent: 5,965,903 →

Application: 09/022,733 →

Low Thermal Expansion Composite Comprising Bodies of Negative Cte Material Disposed Within a Positive Cte Matrix

Patent: 6,326,685 →

Application: 09/072,248 →

Improved Enhanced Lamination Process Between Heatspreader to Pressure Sensitive Adhesive (Psa) Interface as a Step in the Semiconductor Assembly Process

Patent: 6,130,113 →

Application: 09/114,345 →

Laser Marking of Semiconductor Wafer Substrate While Inhibiting Adherence to Substrate Surface of Particles Generated During Laser Marking

Patent: 6,156,676 →

Application: 09/122,335 →

System and Method for Empirically Determining Shrinkage Stresses in a Molded Package and Power Module Employing the Same

Patent: 5,939,641 →

Application: 09/127,707 →

Encapsulated Circuit Using Vented Mold

Patent: 6,319,450 →

Application: 09/351,945 →

Dual Damascene Bond Pad Structure for Lowering Stress and Allowing Circuitry Under Pads

Patent: 6,838,769 →

Application: 09/465,089 →

Electrical Contact and Housing for Use as an Interface Between a Testing Fixture and a Device Under Test

Patent: 6,252,289 →

Application: 09/480,014 →

Method for Reliability Testing Leakage Characteristics in an Electronic Circuit and a Testing Device for Accomplishing the Same

Patent: 6,701,270 →

Application: 09/957,410 →

Flip Chip Semicondustor Device and Method of Making the Same

Patent: 6,830,999 →

Application: 10/173,182 →

Publication: US 2002/0197768

Package Configuration and Manufacturing Method Enabling the Addition of Decoupling Capacitors to Standard Package Designs

Patent: 7,508,062 →

Application: 11/078,052 →

Publication: US 2006/0202303

Device for Minimizing Differential Pair Length Mismatch and Impedance Discontinuities in an Integrated Circuit Package Design

Patent: 7,180,011 →

Application: 11/276,938 →

Reduce or Eliminate Imc Cracking in Post Wire Bonded Dies by Doping Aluminum Used in Bond Pads During Cu/Low-K Beol Processing

Patent: 7,205,673 →

Application: 11/283,044 →

Alternate Pad Structures/Passivation Inegration Schemes to Reduce or Eliminate Imc Cracking in Post Wire Bonded Dies During Cu/Low-K Beol Processing

Patent: 8,552,560 →

Application: 11/283,219 →

Publication: US 2007/0114667

Eliminate Imc Cracking in Post Wirebonded Dies: Macro Level Stress Reduction by Modifying Dielectric/Metal Film Stack in Be Layers During Cu/Low-K Processing

Patent: 7,531,442 →

Application: 11/290,087 →

Publication: US 2007/0123024

Method for Electrical Interconnection Between Printed Wiring Board Layers Using Through Holes with Solid Core Conductive Material

Patent: 8,601,683 →

Application: 11/379,256 →

Publication: US 2006/0175081

Method and Apparatus for Improving Thermal Energy Dissipation in a Direct-Chip-Attach Coupling Configuration of an Integrated Circuit and a Circuit Board

Patent: 7,817,434 →

Application: 11/403,492 →

Publication: US 2006/0211461

Integrated Circuit Chip Assembly Having Array of Thermally Conductive Features Arranged in Aperture of Circuit Substrate

Patent: 7,982,307 →

Application: 11/562,537 →

Publication: US 2008/0116567

Package Configuration and Manufacturing Method Enabling the Addition of Decoupling Capacitors to Standard Package Designs

Patent: 7,829,424 →

Application: 12/174,479 →

Publication: US 2008/0272863

Quad Flat No Lead (Qfn) Integrated Circuit (Ic) Package Having a Modified Paddle and Method for Designing the Package