Patent Assignment
Reel/Frame 035058/0248
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded: 2015-02-20
Received: 2015-02-20
Pages: 96
Assignor
LSI CORPORATION
Executed: 2014-08-04
Assignee
AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
1 YISHUN AVENUE 7, SINGAPORE, SGX, 768923, SINGAPORE
Covered Applications
(73)
High-Reliability Memory
App. No. 12/550,978
→
LED LCD BACKLIGHT WITH LENS STRUCTURE
App. No. 12/546,031
→
REAL TIME SCENE CHANGE DETECTION IN VIDEO SEQUENCES
App. No. 11/950,093
→
LOW MUTUAL INDUCTANCE MATCHED INDUCTORS
App. No. 11/534,340
→
OPTIMIZING FOCUS POINT FOR OPTICAL DISC
App. No. 11/450,846
→
CONTEXT ADAPTIVE BINARY ARITHMETIC DECODING FOR HIGH DEFINITION VIDEO
App. No. 11/331,404
→
METHOD AND APPARATUS FOR POSITIONING BEAM SPOT ON RECORDING MEDIUM
App. No. 11/312,214
→
ASYMMETRIC ALIGNMENT OF SUBSTRATE INTERCONNECT TO SEMICONDUCTOR DIE
App. No. 11/260,334
→
REDUCED DRY ETCHING LAG
App. No. 11/071,903
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METHOD OF IMPLEMENTING AN ENGINEERING CHANGE ORDER IN AN INTEGRATED CIRCUIT DESIGN BY WINDOWS
App. No. 11/015,123
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CELL BUILDER FOR DIFFERENT LAYER STACKS
App. No. 11/010,745
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APPARATUS FOR CONFINING INDUCTIVELY COUPLED SURFACE CURRENTS
App. No. 11/010,970
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INTEGRATED CIRCUIT PACKAGE DESIGN
App. No. 10/979,491
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CONSTRUCTION TO IMPROVE THERMAL PERFORMANCE AND REDUCE DIE BACKSIDE WARPAGE
App. No. 10/954,940
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METHOD OF EARLY PHYSICAL DESIGN VALIDATION AND IDENTIFICATION OF TEXTED METAL SHORT CIRCUITS IN AN INTEGRATED CIRCUIT DESIGN
App. No. 10/947,498
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METHOD AND APPARATUS FOR CANCELING REPEATABLE RUN-OUT ERRORS IN POSITIONING ON RECORDING MEDIUM
App. No. 10/928,493
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OPTICAL DISC CENTER ERROR AMPLITUDE CALIBRATION
App. No. 10/915,232
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PLACEMENT OF A CLOCK SIGNAL SUPPLY NETWORK DURING DESIGN OF INTEGRATED CIRCUITS
App. No. 10/887,599
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PIRACY PROTECTION FOR COMBINED HARDWARE/SOFTWARE PRODUCTS
App. No. 10/709,967
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EMBEDDED PICTURE PSNR/CRC DATA IN COMPRESSED VIDEO BITSTREAM
App. No. 10/812,286
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SAFE METHOD FOR UPGRADING FIRMWARE OF OPTICAL DISK PRODUCT
App. No. 10/771,588
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OPTICAL DISK INITIALIZATION METHOD AND APPARATUS
App. No. 10/737,604
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CELL-BASED METHOD FOR CREATING SLOTTED METAL IN SEMICONDUCTOR DESIGNS
App. No. 10/732,395
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COMMERCIAL DETECTOR WITH A START OF ACTIVE VIDEO DETECTOR
App. No. 10/713,441
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INCREMENTAL DUMMY METAL INSERTIONS
App. No. 10/683,369
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SLOTTED BONDING PAD
App. No. 10/683,101
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ROBUST HIGH DENSITY SUBSTRATE DESIGN FOR THERMAL CYCLING RELIABILITY
App. No. 10/681,554
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VARIABLE GAIN CURRENT FEEDBACK AMPLIFIER
App. No. 10/654,520
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BONDING PAD ISOLATION
App. No. 10/652,453
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METHOD OF CLOCK DRIVEN CELL PLACEMENT AND CLOCK TREE SYNTHESIS FOR INTEGRATED CIRCUIT DESIGN
App. No. 10/650,296
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METHOD FOR PROVIDING CLOCK-NET AWARE DUMMY METAL USING DUMMY REGIONS
App. No. 10/632,622
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INTER-LAYER INTERCONNECTION STRUCTURE FOR LARGE ELECTRICAL CONNECTIONS
App. No. 10/623,082
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VIDEO DECODER AND ENCODER TRANSCODER TO AND FROM RE-ORDERABLE FORMAT
App. No. 10/603,550
→
REAL TIME SCENE CHANGE DETECTION IN VIDEO SEQUENCES
App. No. 10/603,009
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BONDING PAD FOR LOW K DIELECTRIC
App. No. 10/600,255
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2-D LUMA AND CHROMA DMA OPTIMIZED FOR 4 MEMORY BANKS
App. No. 10/458,157
→
VIA AND METAL LINE INTERFACE CAPABLE OF REDUCING THE INCIDENCE OF ELECTRO-MIGRATION INDUCED VOIDS
App. No. 10/400,297
→
DIELECTRIC STACK
App. No. 10/357,142
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METHOD, SYSTEM, AND PRODUCT FOR ACHIEVING OPTIMAL TIMING IN A DATA PATH THAT INCLUDES VARIABLE DELAY LINES AND COUPLED ENDPOINTS
App. No. 10/335,312
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MULTI-LEVEL REDISTRIBUTION LAYER TRACES FOR REDUCING CURRENT CROWDING IN FLIPCHIP SOLDER BUMPS
App. No. 10/327,333
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METHOD AND/OR APPARATUS FOR VIDEO DATA STORAGE
App. No. 10/306,751
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MEMORY VIDEO DATA STORAGE STRUCTURE OPTIMIZED FOR SMALL 2-D DATA TRANSFER
App. No. 10/306,749
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METAL-INSULATOR-METAL CAPACITOR FORMED BY DAMASCENE PROCESSES BETWEEN METAL INTERCONNECT LAYERS AND METHOD OF FORMING SAME
App. No. 10/306,011
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PROGRAMMABLE WRITE SIGNAL GENERATOR
App. No. 10/302,761
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SCATTER DOTS
App. No. 10/293,458
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BONDING PADS OVER INPUT CIRCUITS
App. No. 10/287,668
→
INTER-LAYER INTERCONNECTION STRUCTURE FOR LARGE ELECTRICAL CONNECTIONS
App. No. 10/272,767
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INTEGRATED CIRCUIT PACKAGE DESIGN
App. No. 10/271,003
→
SPECTRAL TRANSLATION FOR VSB COMPENSATION
App. No. 10/260,072
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SOLDER MASK ON BONDING RING
App. No. 10/229,659
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SYSTEM AND METHOD FOR DIRECT MOTION VECTOR PREDICTION IN BI-PREDICTIVE VIDEO FRAMES AND FIELDS
App. No. 10/217,142
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MOTION ESTIMATION METHOD AND SYSTEM FOR MPEG VIDEO STREAMS
App. No. 10/196,731
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APPLICATION OF CO-VERIFICATION TOOLS TO THE TESTING OF IC DESIGNS
App. No. 10/178,193
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ADVANCED HIGH DENSITY DATA WRITE STRATEGY
App. No. 10/171,394
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INTERPOLATOR
App. No. 10/134,741
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METHOD AND DEVICE FOR RECEIVING SEQUENTIAL INSTRUCTIONS
App. No. 10/124,040
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TIME MULTIPLEXING BUS FOR DTV COMMON INTERFACE
App. No. 10/087,111
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THICK TRACES FROM MULTIPLE DAMASCENE LAYERS
App. No. 10/078,233
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ENDIANESS INDEPENDENT MEMORY INTERFACE
App. No. 10/068,680
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ARCHITECTURE FOR A SEA OF PLATFORMS
App. No. 10/044,781
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IMPROVED METHOD FOR AUTONEGOTIATING MULTIPLE DEVICES WITH A SHARED AUTONEGOTIATING CONTROLLER
App. No. 10/021,511
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FAST SAMPLING TEST BENCH
App. No. 09/996,042
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CHIP-OVER-CHIP INTEGRATED CIRCUIT PACKAGE
App. No. 09/993,466
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AHB SEGMENTATION BRIDGE BETWEEN BUSSES HAVING DIFFERENT NATIVE DATA WIDTHS
App. No. 10/000,716
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HEADER DETECT CONFIGURATION WITHIN A DVD-RAM READ DEVICE AND METHODS OF ACQUIRING AND MAINTAINING PHASE LOCK IN A WOBBLE PHASE LOCK LOOP
App. No. 10/002,672
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INTERPOSER FOR SEMICONDUCTOR PACKAGE ASSEMBLY
App. No. 09/974,157
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MOTION COMPENSATED DE-INTERLACING
App. No. 09/965,948
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MICROSTRIP PACKAGE HAVING OPTIMIZED SIGNAL LINE IMPEDANCE CONTROL
App. No. 09/894,210
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THERMAL AND MECHANICAL ATTACHMENT OF A HEATSPREADER TO A FLIP-CHIP INTEGRATED CIRCUIT STRUCTURE USING UNDERFILL
App. No. 09/872,327
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PROCESS FOR REMOVAL OF RESIST MASK OVER LOW K CARBON-DOPED SILICON OXIDE DIELECTRIC MATERIAL OF AN INTEGRATED CIRCUIT STRUCTURE, AND REMOVAL OF RESIDUES FROM VIA ETCH AND RESIST MASK REMOVAL
App. No. 09/873,043
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VIDEO HORIZONTAL AND VERTICAL VARIABLE SCALING FILTER
App. No. 09/855,011
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METHOD FOR MANUFACTURING A DUAL CHIP IN PACKAGE WITH A FLIP CHIP DIE MOUNTED ON A WIRE BONDED DIE
App. No. 09/801,007
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FIELD FREEZE FILTER IMPLEMENTATION
App. No. 09/794,852
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