IP Library Granted Patent US 7,231,626
Granted Patent B2
US 7,231,626 · App. 11/015,123 · Granted Jun 12, 2007

Method of implementing an engineering change order in an integrated circuit design by windows

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Quick Facts
Patent No.
US 7,231,626
App. No.
11/015,123
Granted
Jun 12, 2007
Kind
B2
Abstract

A method of implementing an engineering change order includes steps of: (a) receiving as input an integrated circuit design; (b) receiving as input an engineering change order to the integrated circuit design; (c) creating at least one window in the integrated circuit design that encloses a change to the integrated circuit design introduced by the engineering change order wherein the window is bounded by coordinates that define an area that is less than an entire area of the integrated circuit design; (d) performing a routing of the integrated circuit design that excludes routing of any net that is not enclosed by the window; (e) replacing an area in a copy of the integrated circuit design that is bounded by the coordinates of the window with results of the incremental routing to generate a revised integrated circuit design; and (f) generating as output the revised integrated circuit design.

Claims (20)

1. A method comprising steps of:

(a) receiving as input an integrated circuit design;

(b) receiving as input an engineering change order to the integrated circuit design;

(c) creating at least one window in the integrated circuit design that encloses a change to the integrated circuit design introduced by the engineering change order wherein the window is bounded by coordinates that define an area that is less than an entire area of the integrated circuit design;

(d) performing an incremental routing of the integrated circuit design only for each net in the integrated circuit design that is enclosed by the window;

(e) replacing an area in a copy of the integrated circuit design that is bounded by the coordinates of the window with results of the incremental routing to generate a revised integrated circuit design; and

(f) generating as output the revised integrated circuit design.

2. The method of claim 1 further comprising a step of calculating a net delay only for each net in the integrated circuit design that is enclosed by the window.

3. The method of claim 1 further comprising a step of performing a design rule check only for each net in the integrated circuit design that is enclosed by the window.

4. The method of claim 1 further comprising a step of performing a parasitic extraction only for each net in the integrated circuit design that is enclosed by the window.

5. A computer readable storage medium tangibly embodying instructions for a computer that when executed by the computer implement a method for implementing an engineering change order in an integrated circuit design by windows, the method comprising steps of:

(a) receiving as input an integrated circuit design;

(b) receiving as input an engineering change order to the integrated circuit design;

(c) creating at least one window in the integrated circuit design that encloses a change to the integrated circuit design introduced by the engineering change order wherein the window is bounded by coordinates that define an area that is less than an entire area of the integrated circuit design;

(d) performing an incremental routing only for each net in the integrated circuit design that is enclosed by the window;

(e) replacing an area in a copy of the integrated circuit design that is bounded by coordinates of the window with results of the incremental routing to generate a revised integrated circuit design; and

(f) generating as output the revised integrated circuit design.

6. The computer readable storage medium of claim 5 wherein the method further comprises a step of calculating a net delay only for each net in the integrated circuit design that is enclosed by the window.

7. The computer readable storage meduim of claim 5 wherein the method further comprises a step of performing a design rule check only for each net in the integrated circuit design that is enclosed by the window.

8. The computer readable storage medium of claim 5 wherein the method further comprises a step of performing a parasitic extraction only for each net in the integrated circuit design that is enclosed by the window.

Assignments (11)
RELEASE OF SECURITY INTEREST Recorded Apr 15, 2022
From: CORTLAND CAPITAL MARKET SERVICES LLC
To: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
Reel/Frame 059720/0223 →
SECURITY INTEREST Recorded Feb 1, 2018
From: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
To: CORTLAND CAPITAL MARKET SERVICES LLC, AS COLLATERAL AGENT
Reel/Frame 045216/0020 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2017
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.; BROADCOM CORPORATION
To: BELL SEMICONDUCTOR, LLC
Reel/Frame 044887/0109 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 20, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035058/0248 →
CHANGE OF NAME Recorded Jun 6, 2014
From: LSI LOGIC CORPORATION
To: LSI CORPORATION
Reel/Frame 033102/0270 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 18, 2005
From: HOFF, JASON K.; LAKSHMANAN, VISWANATHAN; JOSEPHIDES, MICHAEL; PREVEDEL, DANIEL W.; BLINNE, RICHARD D.; KUPPINGER, JONATHAN P.
To: LSI LOGIC CORPORATION
Reel/Frame 016816/0196 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2004
From: HOFF, JASON K.; LAKSHMANAN, VISWANATHAN; JOSEPHIDES, MICHAEL; PREVEDEL, DANIEL W.; BLINNE, RICHARD D.; KUPPIGER, JONATHAN P.
To: LSI LOGIC CORPORATION
Reel/Frame 016115/0326 →