Granted Patent B2

US 6,886,147 · App. 10/335,312 · Granted Apr 26, 2005

Abstract

Claims (171)

1. A method for optimizing timing in a circuit after layout of the circuit has been completed, where the circuit includes a variable delay line and coupled endpoint devices, said variable delay line including a plurality of selectable settings, said method comprising the steps of:

varying a current setting of said variable delay line from a maximum setting to a minimum setting;

determining a timing accuracy indicator associated with each one of said plurality of selectable settings as said variable delay line is varied from said maximum setting to said minimum setting;

said timing accuracy indicator including a combination of timing information for each one of said endpoint devices; and

selecting an optimum one of said plurality of selectable settings utilizing said timing accuracy indicator, wherein said optimum one of said plurality of selectable settings is associated with an optimum timing accuracy indicator.

2. The method according to claim 1 , further comprising the steps of:

including a second variable delay line in said circuit, said second variable delay line including a second plurality of selectable settings;

varying a current setting of said second variable delay line from a maximum setting to a minimum setting;

determining a delay inserted by said second variable delay line as said current setting of said second variable delay line is varied from a maximum setting to a minimum setting; and

determining whether said optimum timing accuracy indicator is improved as a delay is inserted by said second variable delay line as said current setting of said second variable delay line is varied from a maximum setting to a minimum setting.

3. The method according to claim 2 , further comprising the steps of:

selecting one of said second plurality of selectable settings which most improves said optimum timing accuracy indicator.

4. The method according to claim 1 , further comprising the steps of:

determining a delay inserted into said circuit by a single buffer;

determining whether said optimum one of said plurality of selectable settings provides passing timing requirements for said circuit; and

in response to a determination that said optimum one of said plurality of selectable settings does not provide passing timing requirements for said circuit, determining a quantity of buffers to be added to said circuit in order for said circuit to have passing timing requirements utilizing said determination of said delay for said single buffer.

5. The method according to claim 4 , further comprising the steps of:

inserting said quantity of buffers in said circuit.

6. The method according to claim 1 , wherein the step of determining a timing accuracy indicator further includes the steps of:

determining a first timing for a first one of said endpoint devices for each one of said plurality of settings;

determining a second timing for a second one of said endpoint devices for each one of said plurality of settings;

adding said first timing to said second timing to produce a total timing for said first and second endpoints combined for each one of said plurality of settings; and

said timing accuracy indicator being said total timing for each one of said plurality of settings, wherein a timing accuracy indicator is associated with each one of said plurality of settings.

7. The method according to claim 6 , further comprising the steps of:

selecting an optimum one of said plurality of settings by determining a timing accuracy indicator that indicates a best total timing, said best total timing being associated with a particular one of said plurality of settings; and

determining that said particular one of said plurality of settings is said optimum one of said plurality of settings.

8. The method according to claim 1 , further comprising the steps of:

determining a first timing for a first one of said endpoint devices for each one of said plurality of settings;

determining whether said first timing is a negative slack;

determining a second timing for a second one of said endpoint devices for each one of said plurality of settings;

determining whether said second timing is a negative slack;

in response to a determination that first and second timings are both negative slacks, adding said first timing to said second timing to produce a total timing for said first and second endpoints combined for each one of said plurality of settings; and

said timing accuracy indicator being said total timing for each one of said plurality of settings, wherein a timing accuracy indicator is associated with each one of said plurality of settings.

9. The method according to claim 1 , further comprising the steps of:

determining a first timing for a first one of said endpoint devices for each one of said plurality of settings;

determining whether said first timing is a negative slack;

determining a second timing for a second one of said endpoint devices for each one of said plurality of settings;

determining whether said second timing is a negative slack;

determining a total timing for said first and second endpoints combined for each one of said plurality of settings by including said first timing in said total timing if said first timing is a negative slack and including said second timing in said total timing if said second timing is a negative slack; and

said timing accuracy indicator being said total timing for each one of said plurality of settings, wherein a timing accuracy indicator is associated with each one of said plurality of settings.

10. The method according to claim 1 , further comprising the steps of:

determining a total negative slack for each one of said plurality of selectable settings, said total negative slack including any negative slack attributable to a first one of said endpoint devices and any negative slack attributable to a second one of said endpoint devices;

said total negative slack being a timing accuracy indicator for each one of said plurality of selectable settings; and

selecting an optimum one of said plurality of settings by selecting one of said plurality of settings that is associated with a particular timing accuracy indicator that indicates a most positive slack, wherein said particular timing accuracy indicator is said optimum timing accuracy indicator.

11. The method according to claim 10 , further comprising the steps of:

including a second variable delay line in said circuit, said second variable delay line including a second plurality of selectable settings;

varying a current setting of said second variable delay line from a maximum setting to a minimum setting;

determining a delay inserted by said second variable delay line as said current setting of said second variable delay line is varied from a maximum setting to a minimum setting; and

determining whether said optimum timing accuracy indicator is improved as a delay is inserted by said second variable delay line as said current setting of said second variable delay line is varied from a maximum setting to a minimum setting.

12. The method according to claim 11 , further comprising the step of:

in response to a determination that said optimum timing accuracy indicator is improved as a delay is inserted by said second variable delay line, selecting a particular one of said second plurality of settings which is associated with a delay inserted by said second variable delay line which most improves said optimum timing accuracy indicator, wherein a revised timing accuracy indicator is obtained.

13. The method according to claim 12 , further comprises the steps of:

determining whether said revised timing accuracy indicator indicates passing timing;

in response to a determination that said revised timing accuracy indicator does not indicate passing timing, determining a delay inserted into said circuit by a single buffer;

determining whether said optimum one of said plurality of selectable settings provides passing timing requirements for said circuit;

in response to a determination that said optimum one of said plurality of selectable settings does not provide passing timing requirements for said circuit, determining a quantity of buffers to be added to said circuit in order for said circuit to have passing timing requirements utilizing said determination of said delay for said single buffer; and

inserting said quantity of buffers to said circuit.

14. A system for optimizing timing in a circuit after layout of the circuit has been completed, where the circuit includes a variable delay line and coupled endpoint devices, said variable delay line including a plurality of selectable settings, comprising:

varying means for varying a current setting of said variable delay line from a maximum setting to a minimum setting;

determining means for determining a timing accuracy indicator associated with each one of said plurality of selectable settings as said variable delay line is varied from said maximum setting to said minimum setting;

said timing accuracy indicator including a combination of timing information for each one of said endpoint devices; and

selecting means for selecting an optimum one of said plurality of selectable settings utilizing said timing accuracy indicator, wherein said optimum one of said plurality of selectable settings is associated with an optimum timing accuracy indicator.

15. The system according to claim 14 , further comprising:

a second variable delay line being included in said circuit, said second variable delay line including a second plurality of selectable settings;

varying means for varying a current setting of said second variable delay line from a maximum setting to a minimum setting;

determining means for determining a delay inserted by said second variable delay line as said current setting of said second variable delay line is varied from a maximum setting to a minimum setting; and

determining means for determining whether said optimum timing accuracy indicator is improved as a delay is inserted by said second variable delay line as said current setting of said second variable delay line is varied from a maximum setting to a minimum setting.

16. The system according to claim 15 , further comprising:

selecting means for selecting one of said second plurality of selectable settings which most improves said optimum timing accuracy indicator.

17. The system according to claim 14 , further comprising:

determining means for determining a delay inserted into said circuit by a single buffer;

determining means for determining whether said optimum one of said plurality of selectable settings provides passing timing requirements for said circuit; and

in response to a determination that said optimum one of said plurality of selectable settings does not provide passing timing requirements for said circuit, determining means for determining a quantity of buffers to be added to said circuit in order for said circuit to have passing timing requirements utilizing said determination of said delay for said single buffer.

18. The system according to claim 17 , further comprising:

said quantity of buffers being inserted in said circuit.

19. The system according to claim 14 , wherein said determining means for determining a timing accuracy indicator further includes:

determining means for determining a first timing for a first one of said endpoint devices for each one of said plurality of settings;

determining means for determining a second timing for a second one of said endpoint devices for each one of said plurality of settings;

adding means for adding said first timing to said second timing to produce a total timing for said first and second endpoints combined for each one of said plurality of settings; and

said timing accuracy indicator being said total timing for each one of said plurality of settings, wherein a timing accuracy indicator is associated with each one of said plurality of settings.

20. The system according to claim 19 , further comprising:

selecting means for selecting an optimum one of said plurality of settings by determining a timing accuracy indicator that indicates a best total timing, said best total timing being associated with a particular one of said plurality of settings; and

determining means for determining that said particular one of said plurality of settings is said optimum one of said plurality of settings.

21. The system according to claim 14 , further comprising:

determining means for determining a first timing for a first one of said endpoint devices for each one of said plurality of settings;

determining means for determining whether said first timing is a negative slack;

determining means for determining a second timing for a second one of said endpoint devices for each one of said plurality of settings;

determining means for determining whether said second timing is a negative slack;

in response to a determination that first and second timings are both negative slacks, adding means for adding said first timing to said second timing to produce a total timing for said first and second endpoints combined for each one of said plurality of settings; and

said timing accuracy indicator being said total timing for each one of said plurality of settings, wherein a timing accuracy indicator is associated with each one of said plurality of settings.

22. The system according to claim 14 , further comprising:

determining means for determining a first timing for a first one of said endpoint devices for each one of said plurality of settings;

determining means for determining whether said first timing is a negative slack;

determining a second timing for a second one of said endpoint devices for each one of said plurality of settings;

determining means for determining whether said second timing is a negative slack;

determining means for determining a total timing for said first and second endpoints combined for each one of said plurality of settings by including said first timing in said total timing if said first timing is a negative slack and including said second timing in said total timing if said second timing is a negative slack; and

said timing accuracy indicator being said total timing for each one of said plurality of settings, wherein a timing accuracy indicator is associated with each one of said plurality of settings.

23. The system according to claim 14 , further comprising:

determining means for determining a total negative slack for each one of said plurality of selectable settings, said total negative slack including any negative slack attributable to a first one of said endpoint devices and any negative slack attributable to a second one of said endpoint devices;

said total negative slack being a timing accuracy indicator for each one of said plurality of selectable settings; and

selecting means for selecting an optimum one of said plurality of settings by selecting one of said plurality of settings that is associated with a particular timing accuracy indicator that indicates a most positive slack, wherein said particular timing accuracy indicator is said optimum timing accuracy indicator.

24. The system according to claim 23 , further comprising:

a second variable delay line being included in said circuit, said second variable delay line including a second plurality of selectable settings;

varying means for varying a current setting of said second variable delay line from a maximum setting to a minimum setting;

determining means for determining a delay inserted by said second variable delay line as said current setting of said second variable delay line is varied from a maximum setting to a minimum setting; and

determining means for determining whether said optimum timing accuracy indicator is improved as a delay is inserted by said second variable delay line as said current setting of said second variable delay line is varied from a maximum setting to a minimum setting.

25. The system according to claim 24 , further comprising:

in response to a determination that said optimum timing accuracy indicator is improved as a delay is inserted by said second variable delay line, selecting means for selecting a particular one of said second plurality of settings which is associated with a delay inserted by said second variable delay line which most improves said optimum timing accuracy indicator, wherein a revised timing accuracy indicator is obtained.

26. The system according to claim 25 , further comprises:

determining means for determining whether said revised timing accuracy indicator indicates passing timing;

in response to a determination that said revised timing accuracy indicator does not indicate passing timing, determining means for determining a delay inserted into said circuit by a single buffer;

determining means for determining whether said optimum one of said plurality of selectable settings provides passing timing requirements for said circuit;

in response to a determination that said optimum one of said plurality of selectable settings does not provide passing timing requirements for said circuit, determining means for determining a quantity of buffers to be added to said circuit in order for said circuit to have passing timing requirements utilizing said determination of said delay for said single buffer; and

inserting means for inserting said quantity of buffers to said circuit.

27. A computer program product in a data processing system for optimizing timing in a circuit after layout of the circuit has been completed, where the circuit includes a variable delay line and coupled endpoint devices, said variable delay line including a plurality of selectable settings, said product comprising:

instruction means for varying a current setting of said variable delay line from a maximum setting to a minimum setting;

instruction means for determining a timing accuracy indicator associated with each one of said plurality of selectable settings as said variable delay line is varied from said maximum setting to said minimum setting;

said timing accuracy indicator including a combination of timing information for each one of said endpoint devices; and

instruction means for selecting an optimum one of said plurality of selectable settings utilizing said timing accuracy indicator, wherein said optimum one of said plurality of selectable settings is associated with an optimum timing accuracy indicator.

28. The product according to claim 27 , further comprising:

instruction means for including a second variable delay line in said circuit, said second variable delay line including a second plurality of selectable settings;

instruction means for varying a current setting of said second variable delay line from a maximum setting to a minimum setting;

instruction means for determining a delay inserted by said second variable delay line as said current setting of said second variable delay line is varied from a maximum setting to a minimum setting; and

instruction means for determining whether said optimum timing accuracy indicator is improved as a delay is inserted by said second variable delay line as said current setting of said second variable delay line is varied from a maximum setting to a minimum setting.

29. The product according to claim 27 , further comprising:

instruction means for selecting one of said second plurality of selectable settings which most improves said optimum timing accuracy indicator.

30. The product according to claim 27 , further comprising:

instruction means for determining a delay inserted into said circuit by a single buffer;

instruction means for determining whether said optimum one of said plurality of selectable settings provides passing timing requirements for said circuit; and

in response to a determination that said optimum one of said plurality of selectable settings does not provide passing timing requirements for said circuit, instruction means for determining a quantity of buffers to be added to said circuit in order for said circuit to have passing timing requirements utilizing said determination of said delay for said single buffer.

31. The product according to claim 30 , further comprising:

instruction means for inserting said quantity of buffers in said circuit.

32. The product according to claim 27 , wherein said instruction means for determining a timing accuracy indicator further includes:

instruction means for determining a first timing for a first one of said endpoint devices for each one of said plurality of settings;

instruction means for determining a second timing for a second one of said endpoint devices for each one of said plurality of settings;

instruction means for adding said first timing to said second timing to produce a total timing for said first and second endpoints combined for each one of said plurality of settings; and

said timing accuracy indicator being said total timing for each one of said plurality of settings, wherein a timing accuracy indicator is associated with each one of said plurality of settings.

33. The product according to claim 32 , further comprising:

instruction means for selecting an optimum one of said plurality of settings by determining a timing accuracy indicator that indicates a best total timing, said best total timing being associated with a particular one of said plurality of settings; and

instruction means for determining that said particular one of said plurality of settings is said optimum one of said plurality of settings.

34. The product according to claim 27 , further comprising:

instruction means for determining a first timing for a first one of said endpoint devices for each one of said plurality of settings;

instruction means for determining whether said first timing is a negative slack;

instruction means for determining a second timing for a second one of said endpoint devices for each one of said plurality of settings;

instruction means for determining whether said second timing is a negative slack;

in response to a determination that first and second timings are both negative slacks, instruction means for adding said first timing to said second timing to produce a total timing for said first and second endpoints combined for each one of said plurality of settings; and

said timing accuracy indicator being said total timing for each one of said plurality of settings, wherein a timing accuracy indicator is associated with each one of said plurality of settings.

35. The product according to claim 27 , further comprising:

instruction means for determining a first timing for a first one of said endpoint devices for each one of said plurality of settings;

instruction means for determining whether said first timing is a negative slack;

instruction means for determining a second timing for a second one of said endpoint devices for each one of said plurality of settings;

instruction means for determining whether said second timing is a negative slack;

instruction means for determining a total timing for said first and second endpoints combined for each one of said plurality of settings by including said first timing in said total timing if said first timing is a negative slack and including said second timing in said total timing if said second timing is a negative slack; and

said timing accuracy indicator being said total timing for each one of said plurality of settings, wherein a timing accuracy indicator is associated with each one of said plurality of settings.

36. The product according to claim 27 , further comprising:

instruction means for determining a total negative slack for each one of said plurality of selectable settings, said total negative slack including any negative slack attributable to a first one of said endpoint devices and any negative slack attributable to a second one of said endpoint devices;

said total negative slack being a timing accuracy indicator for each one of said plurality of selectable settings; and

instruction means for selecting an optimum one of said plurality of settings by selecting one of said plurality of settings that is associated with a particular timing accuracy indicator that indicates a most positive slack, wherein said particular timing accuracy indicator is said optimum timing accuracy indicator.

37. The product according to claim 36 , further comprising:

instruction means for including a second variable delay line in said circuit, said second variable delay line including a second plurality of selectable settings;

instruction means for varying a current setting of said second variable delay line from a maximum setting to a minimum setting;

instruction means for determining a delay inserted by said second variable delay line as said current setting of said second variable delay line is varied from a maximum setting to a minimum setting; and

instruction means for determining whether said optimum timing accuracy indicator is improved as a delay is inserted by said second variable delay line as said current setting of said second variable delay line is varied from a maximum setting to a minimum setting.

38. The product according to claim 37 , further comprising:

in response to a determination that said optimum timing accuracy indicator is improved as a delay is inserted by said second variable delay line, instruction means for selecting a particular one of said second plurality of settings which is associated with a delay inserted by said second variable delay line which most improves said optimum timing accuracy indicator, wherein a revised timing accuracy indicator is obtained.

39. The product according to claim 38 , further comprises:

instruction means for determining whether said revised timing accuracy indicator indicates passing timing;

in response to a determination that said revised timing accuracy indicator does not indicate passing timing, instruction means for determining a delay inserted into said circuit by a single buffer;

instruction means for determining whether said optimum one of said plurality of selectable settings provides passing timing requirements for said circuit;

in response to a determination that said optimum one of said plurality of selectable settings does not provide passing timing requirements for said circuit, instruction means for determining a quantity of buffers to be added to said circuit in order for said circuit to have passing timing requirements utilizing said determination of said delay for said single buffer; and

instruction means for inserting said quantity of buffers to said circuit.

Assignments (9)