Header detect configuration within a DVD-RAM read device and methods of acquiring and maintaining phase lock in a wobble phase lock loop
View Patent ↗In the context of a DVD-RAM read-type architecture in which an optical storage medium ( 20 ) makes use of an eccentric wobble ( 164 ) to attain synchronisation information, a wobble PLL ( 179 ) is held in an acquired state whenever header regions ( 32, 33 ) embossed at regular intervals across the optical storage medium ( 20 ) are detected. More specifically, large dc variations associated with voltage spikes caused by header regions ( 32, 33 ) are scaled ( 260 ) relative to a dynamically varying amplitude envelope of the extracted wobble signal ( 164 ), such as to identify a start location ( 300 ) for each header region. The wobble PLL ( 179 ) is effectively allowed to free-run and hold state during periods of header, thereby mitigating the likelihood that the wobble PLL will loose lock during the header regions. Also, with suspension of the wobble PLL triggered by a first spike ( 300 ), a counter is initiated to over-sample wobble clock periods to pre-empt a successive header and such that the PLL can be disabled immediately prior to the successive header region. Use of a bandpass filter ( 156 ) to extract the wobble signal ( 164 ) benefits from generation of a spike at each transition of the header dc level, which spike can be used as a definitive marker for a header region.
1. A method of synchronizing a phase lock loop to an intermittent clock signal, the method comprising the steps of:
(A) seeking to acquire phase lock of the phase lock loop with the intermittent clock signal during a plurality of first periods of the intermittent clock signal when the intermittent clock signal is present;
(B) timing a duration for each of the first periods;
(C) holding the phase lock loop in a free-running state in advance of and during a plurality of second periods read from a header region on an optical disk when the intermittent clock signal is absent in response to the duration indicating an end to one of the first periods;
(D) identifying re-emergence of the intermittent clock signal; and
(E) seeking to acquire phase lock only after re-emergence of the intermittent clock signal has been validated.
2. The method according to claim 1 , further comprising the step of:
acquiring frequency lock in an asynchronous mode.
3. The method according to claim 1 , wherein the intermittent clock signal is derived from a geometric eccentricity associated with a track on an optical disc and the geometric eccentricity is interspersed by regularly spaced header regions that disrupt the geometric eccentricity.
4. A method of synchronizing a phase lock loop to an intermittent clock signal, the method comprising the steps of:
(A) seeking to acquire phase lock of the phase lock loop with the intermittent clock signal during a plurality of first periods of the intermittent clock signal when the intermittent clock signal is present;
(B) timing a duration for each of the first periods; and
(C) holding the phase lock loop in a free-running state during a plurality of second periods when the intermittent clock signal is absent in response to the duration indicating an end to one of the first periods, wherein the phase lock loop is placed in the free-running state in advance of reading a header region on an optical disk in response to the duration.
5. A method of synchronizing a phase lock loop to an intermittent clock signal, the method comprising the steps of:
(A) seeking to acquire phase lock during periods of the intermittent clock signal;
(B) holding the phase lock loop in a free-running state during periods when the intermittent clock signal is absent;
(C) estimating a signal envelope for the intermittent clock signal; and
(D) bandpass filtering an input signal to generate a plurality of spikes indicative of a transition for a header region on an optical disk.
6. The method according to claim 5 , further comprising the step of:
identifying a relative signal level polarity between a first spike of the spikes and a successive spike of the spikes to identify a requirement for a phase reversal.
7. The method according to claim 5 , further comprising:
filtering the intermittent clock signal in a low pass filter to generate an adaptive slice level signal capable of tracking residual near-DC variations in the intermittent clock signal.
8. The method according to claim 5 , further comprising the step of:
amplifying the signal envelope and the spikes to scale the spikes relative to the signal envelope to differentiate the signal envelope from the spikes.
9. The method according to claim 8 , further comprising the step of:
defining a threshold exceeding the signal envelope.
10. The method according to claim 9 , further comprising the step of:
identifying commencement of the header region by equating a first transition of the spikes through the threshold as being indicative of the header region.
11. A system comprising:
a phase lock loop arranged to receive an intermittent clock signal to which the phase lock loop is to be synchronized, wherein the intermittent clock signal is derived from a geometric eccentricity associated with a track on an optical disc and the geometric eccentricity is interspersed by regularly spaced header regions that disrupt the geometric eccentricity and which each define a data sector; and
a control circuit comprising a counter arranged to time the intermittent clock signal during each of the data sectors, the control circuit configured to (i) maintain operational control of the phase lock loop, (ii) determine a plurality of first periods of time when the intermittent clock signal is stable, (iii) selectively maintain the phase lock loop in a phase acquisition state during the first periods of time, and (iv) force the phase lock loop to enter a free-running state during a plurality of second periods of time when the intermittent clock signal is absent in response to time within each of the data sectors and in advance of an arrival of each of the header regions.
12. A system comprising:
a phase lock loop arranged to receive an intermittent clock signal to which the phase lock loop is to be synchronized;
a control circuit configured to (i) maintain operational control of the phase lock loop, (ii) determine periods of time when the intermittent clocking signal is stable, (iii) selectively maintain the phase lock loop in a phase acquisition state during the periods of time and (iv) force the phase lock loop to enter a free-running state during periods of time when the intermittent clock signal is absent; and
a bandpass filter configured to filter an input signal to generate the intermittent clock signal and a plurality of spikes indicative of a header region of an optical disk.
13. The system of claim 12 , further comprising:
a top hold feedback circuit arranged to estimate a signal envelope for the intermittent clock signal.
14. The system of claim 13 , further comprising:
an amplifier configured to amplify the signal envelope and the spikes, to scale the spikes relative to the signal envelope to differentiate the signal envelope from the spikes.
15. The system of claim 13 , further comprising:
a data slicing circuit configured to define a threshold exceeding the signal envelope.
16. The system of claim 15 , further comprising:
a comparator arrangement configured to identify commencement of the header region by equating a first spike of the spikes transitioning through the threshold as being indicative of the header region.
17. The system of claim 16 , wherein the comparator arrangement comprises a first and a second comparators configured to process opposite signal senses from the signal envelope, the first and the second comparators each providing an output to a controller arranged to identify a relative signal level polarity between the first spike and a successive spike of the spikes to identify a requirement for a phase reversal in the phase lock loop.
18. The system of claim 12 , further comprising:
an array of photodiodes adapted to recover an input signal representation from an optical disc containing data segments interspersed with the header regions.