Metal-insulator-metal capacitor formed by damascene processes between metal interconnect layers and method of forming same
View Patent ↗Within metal interconnect layers above a substrate of an integrated circuit, a vertical metal-insulator-metal (VMIM) capacitor is formed by the same damascene metallization types of processes that formed the metal interconnect layers. The metal interconnect layers have horizontal metal conductor lines, are vertically separated from other metal interconnect layers by an interlayer dielectric (ILD) layer, and electrically connect to the other metal interconnect layers through via connections extending through the ILD layer. One vertical capacitor plate of the VMIM capacitor is defined by a metal conductor line and a via connection. The other vertical capacitor plate is defined by a metal region adjacent to the metal conductor line and the via connection. The metal conductor line, the via connection and the metal region are formed by the damascene metallization processes.
1. A vertical metal-insulator-metal (VMIM) capacitor in an integrated circuit (IC) that has a horizontal substrate, a lower metal interconnect layer and an upper damascene-metallization interconnect layer, the lower metal interconnect layer and the substrate being separated by a dielectric layer, the lower metal interconnect layer and the upper damascene-metallization interconnect layer being separated by an interlayer dielectric (ILD) layer, the upper damascene-metallization interconnect layer being at least partially formed by damascene-metallization steps, comprising:
a first damascene-metallization vertical capacitor plate disposed at least partially within the upper damascene-metallization interconnect layer, the first vertical capacitor plate at least partially formed by the damascene-metallization steps used to form the upper damascene-metallization interconnect layer;
a second damascene-metallization vertical capacitor plate laterally spaced from the first vertical capacitor plate and disposed at least partially within the upper damascene-metallization interconnect layer; and
a capacitor dielectric interposed between the first vertical capacitor plate and the second vertical capacitor plate.
2. A VMIM capacitor as defined in claim 1 wherein:
the first damascene-metallization vertical capacitor plate extends from the upper damascene-metallization interconnect layer at least partially through the ILD layer; and
the second damascene-metallization vertical capacitor plate extends at least partially through the ILD layer.
3. A VMIM capacitor as defined in claim 2 further comprising:
a damascene-metallization conductor line within the upper damascene-metallization interconnect layer;
a damascene-metallization via connection extending between the lower metal interconnect layer and the upper damascene-metallization interconnect layer and electrically connected to the damascene-metallization conductor line, the damascene-metallization conductor line and the damascene-metallization via connection defining a portion of the first vertical capacitor plate; and
a damascene-metallization region horizontally adjacent to the damascene-metallization conductor line and at least a portion of the damascene-metallization via connection and separated from the damascene-metallization conductor line and the damascene-metallization via connection by the capacitor dielectric, the damascene-metallization region defining the second vertical capacitor plate.
4. A VMIM capacitor as defined in claim 3 wherein the damascene-metallization conductor line and the damascene-metallization via connection are integral with each other and formed with dual-damascene metallization process steps.
5. A VMIM capacitor as defined in claim 2 further comprising:
an inner vertical capacitor plate including the second damascene-metallization vertical capacitor plate; and
an outer vertical capacitor plate including the first damascene-metallization vertical capacitor plate and at least partially surrounding the inner vertical capacitor plate.
6. A VMIM capacitor as defined in claim 5 , wherein the first damascene-metallization vertical capacitor plate is positioned on a first side of the second damascene-metallization vertical capacitor plate, further comprising:
a third damascene-metallization vertical capacitor plate positioned on a second side of the second damascene-metallization vertical capacitor plate opposite the first side and separated from the second damascene-metallization vertical capacitor plate by the capacitor dielectric; and
an electrical connection between the first and third damascene-metallization vertical capacitor plates;
and wherein the outer vertical capacitor plate also includes the third damascene-metallization vertical capacitor plate.
7. A VMIM capacitor as defined in claim 6 wherein:
the first damascene-metallization vertical capacitor plate includes:
a first damascene-metallization conductor line within the upper damascene-metallization interconnect layer and disposed on the first side of the second damascene-metallization vertical capacitor plate; and
a first damascene-metallization via connection extending between the lower metal interconnect layer and the upper damascene-metallization interconnect layer, electrically connected to the first damascene-metallization conductor line and disposed on the first side of the second damascene-metallization vertical capacitor plate; and
the third damascene-metallization vertical capacitor plate includes:
a second damascene-metallization conductor line within the upper damascene-metallization interconnect layer and disposed on the second side of the second damascene-metallization vertical capacitor plate; and
a second damascene-metallization via connection extending between the lower metal interconnect layer and the upper damascene-metallization interconnect layer, electrically connected to the second damascene-metallization conductor line and disposed on the second side of the second damascene-metallization vertical capacitor plate.
8. A VMIM capacitor as defined in claim 2 , wherein the second damascene-metallization vertical capacitor plate includes a damascene-metallization region having sidewalls and a bottom side, and the capacitor dielectric at least partially surrounds the sidewalls and bottom side of the damascene-metallization region, further comprising:
a metal liner at least partially surrounding the capacitor dielectric and electrically connected to the first damascene-metallization vertical capacitor plate to form an extension of the first damascene-metallization vertical capacitor plate as an outer capacitor plate.
9. A VMIM capacitor as defined in claim 2 further comprising:
a bottom capacitor plate disposed below the second damascene-metallization vertical capacitor plate and electrically connected to the first damascene-metallization vertical capacitor plate;
and wherein the capacitor dielectric is also interposed between the second damascene-metallization vertical capacitor plate and the bottom capacitor plate.
10. A VMIM capacitor as defined in claim 9 wherein the bottom capacitor plate is integrated in the lower metal interconnect layer.
11. A VMIM capacitor as defined in claim 2 wherein:
the lower metal interconnect layer includes metal conductor lines underlying the ILD layer excluding a region below the second damascene-metallization vertical capacitor plate.
12. A VMIM capacitor as defined in claim 2 , wherein the IC also has a second upper damascene-metallization interconnect layer and a second ILD layer in addition to the upper damascene-metallization interconnect layer and the ILD layer first aforesaid, the second upper damascene-metallization interconnect layer being above the first upper damascene-metallization interconnect layer and separated therefrom by at least the second ILD layer, the second upper damascene-metallization interconnect layer being at least partially formed by second damascene-metallization steps in addition to the damascene-metallization steps first aforesaid, further comprising:
a third damascene-metallization vertical capacitor plate disposed within the second upper damascene-metallization interconnect layer and at least partially through the second ILD layer, the third vertical capacitor plate at least partially formed by the second damascene-metallization steps used to form the second upper damascene-metallization interconnect layer;
a fourth damascene-metallization vertical capacitor plate laterally spaced from the third vertical capacitor plate and disposed within the second upper damascene-metallization interconnect layer and at least partially through the second ILD layer;
a second capacitor dielectric in addition to the capacitor dielectric first aforesaid interposed between the third vertical capacitor plate and the fourth vertical capacitor plate;
a first electrical connection between the first and third damascene-metallization vertical capacitor plates; and
a second electrical connection between the second and fourth damascene-metallization vertical capacitor plates;
and wherein the first and third damascene-metallization vertical capacitor plates form a first stacked capacitor plate of the VMIM capacitor, and the second and fourth damascene-metallization vertical capacitor plates form a second stacked capacitor plate of the VMIM capacitor.
13. A VMIM capacitor as defined in claim 2 further comprising:
a third damascene-metallization vertical capacitor plate disposed within the upper damascene-metallization interconnect layer and at least partially through the ILD layer, the third vertical capacitor plate at least partially formed by the damascene-metallization steps used to form the upper damascene-metallization interconnect layer, the third vertical capacitor plate laterally spaced from the first vertical capacitor plate;
a fourth damascene-metallization vertical capacitor plate laterally spaced from the third vertical capacitor plate and disposed within the upper damascene-metallization interconnect layer and at least partially through the ILD layer;
a first electrical connection between the first and third damascene-metallization vertical capacitor plates; and
a second electrical connection between the second and fourth damascene-metallization vertical capacitor plates;
and wherein the capacitor dielectric is also interposed between the third vertical capacitor plate and the fourth vertical capacitor plate, the first and third damascene-metallization vertical capacitor plates form a first side-by-side capacitor plate of the VMIM capacitor and the second and fourth damascene-metallization vertical capacitor plates form a second side-by-side capacitor plate of the VMIM capacitor.
14. In a vertical metal-insulator-metal (VMIM) capacitor formed at least partially in an interlayer dielectric (ILD) layer between horizontal first and second metal interconnect layers in an integrated circuit (IC), the first metal interconnect layer being separated from a substrate of the IC by at least one dielectric layer, the first and second metal interconnect layers being connected by a via extending substantially vertically through the ILD layer, the VMIM capacitor comprising first and second substantially vertical plates separated by capacitor dielectric material, and an improvement wherein:
one of the plates of the capacitor is formed by a vertical surface of the via.