Placement of a clock signal supply network during design of integrated circuits
View Patent ↗A method of placing a clock signal supply network in a design representation for an integrated circuit. The design representation may comprise a plurality of clockable circuit cells. The method may comprise identifying a first of the clockable circuit cells in the design representation. The method may further comprise identifying a second of the clockable circuit cells in the design representation. The second clockable circuit cell may have a clock timing dependent relation relative to the first clockable circuit cell. The method may further comprise configuring the clock signal supply network. The clock signal supply network may be configured to supply respective clock signals to the first and said second clockable circuit cells. The clock signal supply network may be configured to route the respective clock signals such that a timing difference between the respective clock signals is protected from process, voltage and temperature (PVT) influences.
1. A method of placing a clock signal supply network in a design representation for an integrated circuit, the design representation comprising a plurality of clockable circuit cells, and the method comprising the steps of:
(a) identifying a first of said clockable circuit cells configured to receive a first of a plurality of respective clock signals controllable by a first combinatorial logic of said clock signal supply network;
(b) identifying a second of said clockable circuit cells configured to receive a second of said respective clock signals, said second clockable circuit cell having a clock timing dependent relation relative to said first clockable circuit cell that defines a cell cluster; and
(c) duplicating said first combinatorial logic to create a second combinatorial logic of said clock signal supply network within said cell cluster to supply said second respective clock signal to said second clockable circuit cell.
2. The method of claim 1 , wherein said design representation comprises a first location for said first clockable circuit cell and a second location for said second clockable circuit cell, said second location being non-adjacent to said first location.
3. The method of claim 1 , further comprising the step of:
inserting in said clock supply network a common portion coupled to said first combinatorial logic and said second combinatorial logic.
4. The method of claim 3 , wherein said cell cluster comprises no repeater cells.
5. The method of claim 1 , wherein said respective clock signals comprise a common clock signal for said first clockable circuit cell and said second clockable circuit cell.
6. The method of claim 1 , wherein said second clockable circuit cell is configured to receive a signal from an output of said first clockable circuit cell.
7. The method of claim 1 , further comprising the step of:
routing a first clock supply path for said first clockable circuit cell and a second clock supply path for said second clockable cell in a closely adjacent relationship.
8. The method of claim 1 , wherein step (a) comprises the sub-steps of:
identifying at least one signal path that passes through plural ones of said plurality of clockable circuit cells;
identifying said first clockable circuit cell at a first end of said signal path; and
identifying said second clockable circuit cell at a second end of said signal path.
9. The method of claim 8 , further comprising the step of:
identifying a particular clock node of a plurality of clock nodes in said clock signal supply network, wherein said particular clock node (i) represents a common source from which said respective clock signals for said first clockable circuit cell and said second clockable circuit cell are derived and (ii) is closest among said clock nodes to said first clockable circuit cell and said second clockable circuit cell.
10. The method according to claim 1 , further comprising the step of:
routing said respective clock signals such that a timing difference between said respective clock signals is protected from process, voltage and temperature (PVT) influences.
11. The method according to claim 1 , further comprising the step of:
allocating a third of said clockable circuit cells to said first cell cluster, said third clockable circuit cell lacking said clock timing dependent relation relative to said first clockable circuit cell.
12. A computer based design tool for placing a clock signal supply network in a design representation for an integrated circuit, the design representation comprising a plurality of clockable circuit cells, and the tool being configured to:
(a) identify a first of said clockable circuit cells configured to receive a first of a plurality of respective clock signals controllable by a first combinatorial logic of said clock signal supply network;
(b) identify a second of said clockable circuit cells configured to receive a second of said respective clock signals, said second clockable circuit cell having a clock timing dependent relation relative to said first clockable circuit cell that defines a cell cluster; and
(c) duplicate said first combinatorial logic to create a second combinatorial logic of said clock signal supply network within said cell cluster to supply said second respective clock signal to said second clockable circuit cell.
13. The tool of claim 12 , wherein said tool is further configured to:
insert in said clock supply network a common portion coupled to said first combinatorial logic and said second combinatorial logic.
14. The tool of claim 12 , wherein said tool is further configured to:
route a first clock supply path for said first clockable circuit cell and a second clock supply path for said second clockable cell in a closely adjacent relationship.
15. An integrated circuit comprising:
a plurality of clockable circuit cells including (i) a first clockable circuit cell within a first cell cluster and (ii) both a second clockable circuit cell and a third clockable circuit cell within a second cell cluster, said third clockable circuit cell having a clock timing dependent relation relative to said second clockable circuit cell; and
a clock supply network for supplying a plurality of respective clock signals to said clockable circuit cells, said clock supply network comprises (i) a first combinatorial logic configured to controllably supply a first of said respective clock signals to said first clockable circuit cell, (ii) a second combinatorial logic within said second cluster to controllably supply a second of said respective clock signals to said second clockable circuit cell, wherein said second combinatorial logic duplicates said first combinatorial logic and (iii) a design such that a timing difference between said respective clock signals is protected from process, voltage and temperature (PVT) influences.
16. The integrated circuit of claim 15 , wherein said second clockable circuit cell and said third clockable circuit cell are located at non-adjacent locations.
17. The integrated circuit of claim 15 , wherein said clock supply network further comprises a common portion coupled to said first combinatorial logic and said second combinatorial logic.
18. The integrated circuit of claim 15 , wherein said clock supply network further comprises a first clock signal path and a second clock signal path for supplying said respective clock signals to said second clockable circuit cell and said third clockable circuit cell, said first signal path and said second signal path being routed to be closely adjacent each other.
19. The integrated circuit according to claim 15 , wherein said first combinatorial logic comprises a clock gate.
20. The integrated circuit according to claim 15 , wherein said first combinatorial logic comprises a clock multiplexer.