Via and metal line interface capable of reducing the incidence of electro-migration induced voids
Embodiments of the invention include a method for forming copper interconnect structure. The method involves providing a substrate having a copper conductive layer formed thereon. An insulating layer having openings is formed on the conductive layer so that the openings expose portions of the underlying conductive layer at the bottom of the openings. A barrier layer is formed on the surface of the substrate. A portion of the barrier layer is removed at the bottom of the opening to expose the underlying conductive layer. A copper plug is formed in the opening such that the bottom of the plug is in contact with the exposed conductive layer. The substrate can be subjected to further processing if desired. The invention also includes a copper interconnect structure having increased resistance to electromigration.
1. A method for forming a robust copper interconnect structure having increased resistance to void failure, the method comprising:
a) providing a substrate having a conductive layer formed thereon, the conductive layer comprising a copper-containing material and having an insulating layer formed thereon, the insulating layer having an opening that exposes a portion of the underlying conductive layer at the bottom of the opening;
b) forming a barrier layer on the substrate so that the barrier layer is formed on the insulating layer and on the exposed portion of the conductive layer in the opening;
c) removing a portion of the barrier layer at the bottom of the opening to expose the underlying conductive layer by anisotropically etching the barrier layer to expose the conductive layer at the bottom of the opening; and
d) forming a conductive plug with a copper-containing material in the opening such that the bottom of the plug is in contact with the exposed conductive layer.
2. The method as in claim 1 wherein the operation of a) providing a substrate includes providing a substrate having a second barrier layer formed between the conductive layer and the insulating layer; and
wherein anisotropically etching includes anisotropically etching the barrier layer and the second barrier layer at the bottom of the opening to expose the conductive layer.
3. The method as in claim 1 wherein the operation of anisotropically etching the metal barrier layer at the bottom of the opening comprises one of plasma etching, reactive ion etching, and flood ion beam sputtering techniques.
4. The method as in claim 1 wherein the operation of anisotropically etching the metal barrier layer at the bottom of the opening comprises plasma etching the metal barrier layer with an etch chemistry that includes at least one of argon, hydrogen, C z H y F x , and SF x .
5. The method of claim 1 wherein the insulating layer is comprised of a low-K dielectric material.
6. The method of claim 1 wherein the method is used to form electrical interconnect structures on a semiconductor chip.
7. The method of claim 1 , wherein the opening is a via.
8. The method as in claim 1 wherein the operation of b) forming the barrier layer includes pre-cleaning the substrate using a plasma formed by igniting at least one argon, hydrogen, and C x H y F z , into the plasma and then forming the metal barrier layer over the pre-cleaned substrate.
9. The method as in claim 1 wherein the operation of b) forming the barrier layer comprises forming the metal barrier layer such that the portions of the barrier layer on the insulating layer and on the sidewalls of the opening are thicker than the portion of the barrier layer on the bottom of the opening.
10. The method as in claim 9 wherein forming the metal barrier layer is accomplished using physical vapor depositing a barrier material at an angle.
11. The method as in claim 9 wherein the operation of anisotropically etching the metal barrier layer at the bottom of the opening is accomplished using a technique selected from among reactive ion etching, plasma etching, flood ion beam sputtering techniques.
12. The method as in claim 1 wherein the operation of anisotropically etching the metal barrier layer at the bottom of the opening is accomplished using a technique selected from among reactive ion etching, plasma etching, flood ion beam sputtering techniques.
13. The method as in claim 11 wherein the operation of anisotropically etching the metal barrier layer at the bottom of the opening comprises plasma etching the metal barrier layer with an etch chemistry that includes at least one of argon, hydrogen, C z H y F x , and SF x .
14. The method of claim 11 wherein the insulating layer is comprised of a low-K dielectric material.
15. The method of claim 11 wherein the method is used to form electrical interconnect structures on a semiconductor chip.
16. A semiconductor integrated circuit formed using the method described in claim 11 .
17. The method of claim 11 , wherein the opening is a via.