IP Library Granted Patent US 6,906,595
Granted Patent B2
US 6,906,595 · App. 10/654,520 · Granted Jun 14, 2005

Variable gain current feedback amplifier

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Quick Facts
Patent No.
US 6,906,595
App. No.
10/654,520
Granted
Jun 14, 2005
Kind
B2
Abstract

An apparatus comprising an amplifier, a first resistor and a second resistor. The amplifier (i) comprises a first transistor and a second transistor and (ii) may be configured to generate an output signal in response to an input signal. The first resistor may be connected between an emitter of the second transistor and a signal ground. The second resistor may be connected between the emitter of the second transistor and a base of the first transistor. A gain of the amplifier may be adjusted by varying a value of the first resistor and a value of the second resistor.

Claims (34)

1. An apparatus comprising:

an amplifier (i) comprising a first transistor and a second transistor and (ii) configured to generate an output signal on an output node in response to an input signal, wherein said amplifier comprises a differential amplifier;

a first resistor connected between an emitter of said second transistor and a signal ground; and

a second resistor connected between said emitter of said second transistor and a base of said first transistor, wherein a gain of said amplifier is adjusted by varying a value of said first resistor and a value of said second resistor.

2. The apparatus according to claim 1 , wherein said apparatus further comprises (i) a third transistor connected between a supply voltage and a collector of said first transistor and (ii) a third resistor connected between said supply voltage and a collector of said second transistor.

3. The apparatus according to claim 1 , wherein said apparatus further comprises an input resistor connected between said base of said first transistor and said input signal.

4. The apparatus according to claim 2 , wherein said third resistor is implemented as a fourth transistor and a fifth transistor.

5. The apparatus according to claim 4 , wherein said apparatus further comprises a fifth resistor connected between said output node and said signal ground.

6. The apparatus according to claim 1 , wherein said first resistor comprises a plurality of transistors.

7. The apparatus according to claim 6 , wherein said second resistor comprises a plurality of transistors.

8. The apparatus according to claim 7 , wherein said plurality of transistors enables a resistor pair in response to a first and second control signal.

9. The apparatus according to claim 8 , wherein said first control signal enables a first resistor of said resistor pair and said second control enables a second resistor of said resistor pair.

10. An apparatus comprising:

an amplifier (i) comprising a transistor and a gain stage and (ii) configured to generate an output signal on an output node in response to an input signal;

a first resistor comprising a plurality of transistors connected between an emitter of said transistor and a signal ground; and

a second resistor connected between said emitter of said transistor and an input of said gain stage, wherein a gain of said amplifier is adjusted by varying a value of said first resistor and a value of said second resistor.

11. The apparatus according to claim 1 , wherein:

said first resistor comprises a first continuously variable resistive element adjustable in response to a first analog control signal; and

said second resistor comprises a second continuously variable resistive element adjustable in response to a second analog control signal.

12. The apparatus according to claim 1 , wherein:

said first resistor comprises a first plurality of digital resistive elements, when one or more of said digital resistive elements are enabled in response to a first digital control signal; and

said second resistor comprises a second plurality of digital resistive elements, when one or more of said digital resistive elements are enabled in response to a second digital control signal.

13. The apparatus according to claim 12 , wherein said first digital and control signals comprise a multi-bit control signals.

14. The apparatus according to claim 10 , wherein said amplifier comprises a differential amplifier.

15. A method for controlling an amplifier comprising the steps of:

(A) implementing an amplifier (i) comprising a first transistor and a second transistor and (ii) configured to generate an output signal in response to an input signal;

(B) implementing a first resistor connected between an emitter of said second transistor and a signal ground; and

(C) implementing a second resistor connected between said emitter of said second transistor and a base of said first transistor, wherein a gain of said amplifier is adjusted by varying a value of said first resistor and a value of said second resistor controlled by (i) one or more multi-bit digital control signals and (ii) one or more multi-bit analog control signals.

16. The method according to claim 15 , wherein:

said first resistor comprises a first continuously variable resistive element adjustable in response to a first of said analog control signals; and

said second resistor comprises a second continuously variable resistive element adjustable in response to a second of said analog control signals.

17. The method according to claim 15 , wherein:

said first resistor comprises a first plurality of digital resistive elements, when one or more of said digital resistive elements are enabled in response to a first of said digital control signals; and

said second resistor comprises a second plurality of digital resistive elements, when one or more of said digital resistive elements are enabled in response to a second of said digital control signals.

Assignments (9)
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 047196 FRAME: 0097. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 6, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048555/0510 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047196/0097 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 20, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035058/0248 →
CHANGE OF NAME Recorded Jun 6, 2014
From: LSI LOGIC CORPORATION
To: LSI CORPORATION
Reel/Frame 033102/0270 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 30, 2003
From: KIM, HEUNG; LYNN, LAPOE E.
To: LSI LOGIC CORPORATION
Reel/Frame 014464/0563 →