Method of fabricating a package for a micro component
View Patent ↗Techniques are disclosed for fabricating a relatively thin package for housing a micro component, such as an opto-electronic or MEMs device. The packages may be fabricated in a wafer-level batch process. The package may include hermetically sealed feed-through electrical connections coupling the micro component to electrical contacts on an exterior surface of the package.
1. A method of fabricating a package for a micro component, the method comprising:
bonding a first wafer to a second wafer so that the micro component is located in an area defined by the first and second wafers, wherein the first wafer includes feed-through metallization that at least partially fills micro-vias from the front-side of the first wafer, and wherein the feed-through metallization forms part of one or more electrically conductive paths to or from the micro component when the first and second wafers are bonded together;
providing cavities in the back-side of the first wafer opposite the micro-vias in the front-side of the first wafer;
providing electrically conductive contacts on the back-side of the first wafer that are electrically coupled to the feed-through metallization; and
subsequently thinning the first wafer from its back-side, wherein forming the cavities and providing the conductive contacts is performed before thinning the back-side of the first wafer.
2. The method of claim 1 wherein said thinning includes thinning the first wafer to a thickness of 200 μm or less.
3. The method of claim 1 wherein said thinning includes thinning the first wafer to a thickness of 100 μm or less.
4. The method of claim 1 including thinning the first wafer to a thickness of less than 50% its original thickness.
5. The method of claim 1 wherein thinning the back-side of the first wafer includes using a mechanical process.
6. The method of claim 1 wherein thinning the back-side of the first wafer includes grinding the back-side of the first wafer.
7. The method of claim 1 wherein the micro component is mounted on or integrated with the second wafer.
8. The method of claim 7 including providing a cavity in the front-side of the first wafer to provide room for the micro component.
9. The method of claim 1 wherein the micro component is mounted to or integrated with the first wafer.
10. The method of claim 9 including providing a cavity in the front-side of the second wafer to provide room for the micro component.
11. The method of claim 1 wherein the first wafer comprises a semiconductor material and the second wafer comprises a glass or semiconductor material.
12. The method of claim 1 wherein the method is part of a wafer-level batch process.
13. The method of claim 1 wherein at least one of the wafers is an SOI wafer.
14. The method of claim 1 wherein at least one of the wafers includes a semiconductor layer on an isolating layer.
15. A method of fabricating a package for a micro component, the method comprising:
bonding a first wafer to a second wafer so that the micro component is located in an area defined by the first and second wafers, wherein the first wafer includes feed-through metallization that at least partially fills micro-vias from the front-side of the first wafer, and wherein the feed-through metallization forms part of one or more electrically conductive paths to or from the micro component when the first and second wafers are bonded together;
subsequently thinning the first wafer from its back-side,
removing material from the back-side of the first wafer, after said thinning, to expose the feed-through metallization, wherein removing material from the back-side of the first wafer includes forming cavities in the back-side of the first wafer and partially etching away a buried oxide layer or other isolating etch stop layer to expose the feed-through metallization; and
providing electrical contacts at the back-side of the first wafer to contact the exposed feed-through metallization.
16. A method of fabricating a package for a micro component, the method comprising:
bonding a first wafer to a second wafer so that the micro component is located in an area defined by the first and second wafers, wherein the first wafer includes feed-through metallization that at least partially fills micro-vias from the front-side of the first wafer, and wherein the feed-through metallization forms part of one or more electrically conductive paths to or from the micro component when the first and second wafers are bonded together;
forming, prior to bonding the first and second wafers together, shallow grooves in the front-side of the first wafer adjacent an area for the micro component; and
forming a respective one of the micro-vias in each of the shallow grooves toward an end of the groove that is further from the area for the micro component.