Method of operating a stacked spin based memory
View Patent ↗A method of operating a spin based memory cell stacked architecture is provided. The cells are comprised of magnetic spin storage elements stacked on top of each other on a silicon substrate, as well as one or two semiconductor FET isolation elements.
1. A method of operating a multi-bit magnetoelectronic memory device comprising:
providing a stacked arrangement of separate magnetic spin based memory elements over a semiconductor substrate;
wherein each of said magnetic spin based memory elements stores at least one bit of data in the form of an electron spin state associated with a ferromagnetic layer, so that a plurality of separate data bits can be stored in said stacked arrangement of separate magnetic memory elements in the form of a plurality of separate electron spin states;
addressing and reading said stacked arrangement of separate magnetic spin based memory elements so that said plurality of separate electron spin states can be read out at the same time.
2. The method of claim 1 , wherein each magnetic spin based memory element is a three terminal magnetic spin transistor.
3. The method of claim 1 , further including a step: coupling at least one semiconductor isolation element to said stacked arrangement of separate magnetic spin based memory elements.
4. The method of claim 3 , wherein said semiconductor isolation element is a field effect transistor.
5. The method of claim 1 , wherein an entire byte worth of data can be read at once from said stack arrangement of magnetic spin based memory elements.
6. The method of claim 1 , including a step of providing a separate layer for each magnetic spin based memory element in said stacked arrangement.
7. A method of providing a multi-layer magnetoelectronic memory device comprising:
providing a plurality of separate ferromagnetic layers in a stacked arrangement situated on a silicon based substrate;
wherein each of said plurality of separate ferromagnetic layers stores at least one bit of data in the form of an electron spin state, so that a plurality of data bits can be stored in said stacked arrangement;
providing at least one low transmission barrier layer in said stacked arrangement;
reading all of said plurality of data bits at the same time.
8. The method of claim 7 , wherein each magnetic spin based memory element is a three terminal magnetic spin transistor.
9. The method of claim 7 , further including a first semiconductor isolation element which isolates said stacked arrangement.
10. The method of claim 7 , further including a step: providing a plurality of second separate ferromagnetic layers, each of which is coupled to an associated one of said plurality of separate ferromagnetic layers, such that said one bit of data is related to a relative magnetization state of a pair of one of said plurality of separate ferromagnetic layers and one of said second separate ferromagnetic layers.
11. The method of claim 7 , further including a plurality of thin film semiconductor isolation elements situated in layers between said plurality of magnetic spin based memory elements.
12. The method of claim 7 , wherein said separate ferromagnetic layers are separated by insulating layers.
13. A method of operating a multi-layer magnetoelectronic memory device comprising:
providing a plurality of separate magnetic spin based memory elements situated in a stacked arrangement on a semiconductor substrate;
wherein said each of said plurality of separate magnetic spin based memory elements includes a plurality of separate corresponding storage layers;
providing a plurality of separate insulating layers interposed between said separate corresponding storage layers for insulating said separate magnetic spin based memory elements;
wherein each magnetic spin based memory element stores a bit of data in the form of an electron spin state associated with a ferromagnetic layer, so that a plurality of data bits can be stored in said magnetic memory elements in the form of a plurality of separate electron spin states;
further wherein each magnetic spin based memory element includes a unique transimpedance compared to other magnetic spin based memory elements in said stack arrangement;
reading all of said plurality of separate magnetic spin based memory elements at the same time in said stacked arrangement.
14. The method of claim 13 , wherein multiple data bits can be read out at the same time by deconvolving an output voltage of the magnetoelectronic memory device to determine a value of individual bits for each magnetic spin based memory element.
15. The method of claim 13 , wherein each of said plurality of magnetic spin based memory elements includes a magnetic spin transistor with an associated ferromagnetic collector, ferromagnetic emitter, and base.
16. The method of claim 13 , further providing a semiconductor isolation element to isolate an output of such device.
17. The method of claim 13 , wherein said semiconductor isolation element is a field effect transistor.
18. The method of claim 17 , wherein each of said plurality of magnetic spin based memory elements includes a low transmission barrier.
19. The method of claim 17 , wherein said field effect transistor is situated in a thin film layer.
20. The method of claim 13 , wherein said unique transimpedance is set by configuring a base material associated with each of said magnetic spin based memory elements.