Schottky diode device with aluminum pickup of backside cathode
View Patent ↗An integrated circuit package includes a semiconductor chip having a passivation layer forming the top surface of the semiconductor chip and a metal pad formed on the passivation layer and a discrete electronic device having a first terminal formed on a first surface and a second terminal formed on a second surface opposite the first surface of the discrete electronic device where the first surface of the discrete electronic device is attached to the metal pad using a conductive adhesive structure. The semiconductor chip and the discrete electronic device are encapsulated in an encapsulation material. An electrical connection is formed between the metal pad and one of a bond pad of the semiconductor chip or a package post of the integrated circuit package. In one embodiment, the metal pad is an aluminum pad and a metal line connects the metal pad to a bond pad of the semiconductor chip.
1. A method for forming an integrated circuit package including a semiconductor chip having a passivation layer and a discrete electronic device, the method comprising:
providing a discrete electronic device having a first surface and a second surface opposite the first surface, the first surface comprising a single terminal being a backside electrode of the discrete electronic device, and the second surface comprises a second terminal, at least one of the backside electrode and the second terminal of the discrete electronic device being electronically coupled to the semiconductor chip;
forming a metal pad on the top surface of the passivation layer of the semiconductor chip;
attaching substantially the entire first surface of the discrete electronic device to the metal pad using a conductive adhesive structure to form an electrical connection between the backside electrode of the discrete electronic device and the metal pad;
forming an electrical connection from the metal pad to one of a bond pad of the semiconductor chip or a package post of the integrated circuit package; and
encapsulating the semiconductor chip and the discrete electronic device to form the integrated circuit package.
2. The method of claim 1 , wherein forming an electrical connection from the metal pad to one of a bond pad of the semiconductor chip or a package post of the integrated circuit package comprises forming an electrical connection from the metal pad to a first bond pad of the semiconductor chip.
3. The method of claim 2 , wherein forming an electrical connection from the metal pad to a first bond pad of the semiconductor chip comprises:
forming a metal line on the top surface of the passivation layer of the semiconductor chip, the metal line connecting the metal pad to the first bond pad.
4. The method of claim 3 , wherein the first bond pad connects to circuitry of the semiconductor chip.
5. The method of claim 1 , wherein forming an electrical connection from the metal pad to one of a bond pad of the semiconductor chip or a package post of the integrated circuit package comprises forming an electrical connection from the metal pad to a first package post of the integrated circuit package.
6. The method of claim 5 , wherein forming an electrical connection from the metal pad to a first package post of the integrated circuit package comprises:
connecting the metal pad to the first package post using a bond wire.
7. The method of claim 1 , further comprising:
forming a second electrical connection using a bond wire from the second terminal on the second surface of the discrete electronic device to one of a bond pad of the semiconductor chip or a package post of the integrated circuit package.
8. The method of claim 1 , wherein the metal pad comprises an aluminum pad.
9. The method of claim 1 , wherein the conductive adhesive structure comprises a conductive epoxy.
10. The method of claim 9 , wherein the conductive adhesive structure comprises a gold layer formed on the first surface of the discrete electronic device and a conductive epoxy layer formed on the gold layer for attaching to the metal pad.
11. The method of claim 10 , wherein the gold layer is doped with 0.1% arsenic.
12. The method of claim 1 wherein the discrete electronic device comprises one of a Schottky diode, a VDMOS device, an NPN transistor and a PNP transistor.
13. The method of claim 1 , further comprising:
prior to attaching the first surface of the discrete electronic device to the metal pad, roughening the first surface of the discrete electronic device using a coarse wheel grinder.