Modeling resolution enhancement processes in integrated circuit fabrication
A Wafer Image Modeling and Prediction System (“WIMAPS”) is described that includes systems and methods that generate and/or apply models of resolution enhancement techniques (“RET”) and printing processes in integrated circuit (“IC”) fabrication. The WIMAPS provides efficient processes for use by designers in predicting the RET and wafer printing process so as to allow designers to filter predict printed silicon contours prior to application of RET and printing processes to the circuit design.
1. A method for compensating dimensional variations between a contour of a predicted wafer contour model and an as-designed contour of a circuit design layout comprising:
generating, via a computer system, a wafer printing model from the circuit design layout using a resolution enhancement technology (RET) model;
generating an inverse RET model from the wafer printing model, wherein the inverse RET model is an approximate inverse of the wafer printing model;
generating the predicted wafer contour model by combining the inverse RET model with the wafer printing model;
determining a difference of a lateral dimension of the contour of the predicted wafer contour model and the as-designed contour of the circuit design layout, wherein the lateral dimension is parallel to a wafer surface of the predicted wafer; and
modifying the circuit design layout to reduce the difference in the lateral dimension.
2. The method of claim 1 , wherein the difference in lateral dimension comprises a lateral dimension deviation of two critical dimensions.
3. The method of claim 2 , wherein the critical dimension comprises a distance between bridges, a via enclosure dimension, or a gate endcap pullback dimension.
4. The method of claim 1 , wherein the determining further comprises minimizing a difference of a hot spots, sensitivity, mask error enhancement-factor, and normalized image log slope between the predicted wafer contour model and the as-designed contour of the circuit design layout.
5. The method of claim 4 , wherein the minimizing is a non-linear optimization problem.
6. The method of claim 1 , wherein the predicted wafer contour model is represented by an expression
P*P −1 ,
wherein P is the wafer printing model and P −1 is the inverse RET model.
7. The method of claim 6 , wherein the predicted wafer contour model is represented by an expression
|P*P −1 −I|,
wherein I is an identity model representing an as-designed circuit layout.
8. The method of claim 6 , wherein the predicted wafer contour model is represented by an expression
|P*P −1 −I|+μ|P*P −1 d−s|,
wherein μ is a weighting variable, d is a lateral dimension of a contour of the predicted wafer contour model, and s is a measured lateral dimension of an actual silicon contour.
9. A method for compensating lithographic variations comprising:
generating, via a computer system, a predicted wafer contour model by combining an inverse RET model with a wafer printing model, wherein the inverse RET model is an approximate inverse of the wafer printing model, wherein the predicted wafer contour model is represented by an expression P*P −1 , wherein P comprises the wafer printing model and P −1 comprises the inverse of the wafer printing model;
minimizing a difference equation represented by an expression |P*P −1 −I|, wherein I comprises an as intended circuit contour model, and wherein |P*P −1 −I| comprises a variation between a first lateral dimension of the predicted wafer contour model and a second lateral dimension of the as intended circuit contour model; and
modifying the inverse of the wafer printing model, P −1 , based on the minimization.
10. The method of claim 9 , further comprising:
generating the wafer printing model from a circuit design layout using a resolution enhancement technology (RET) model; and
generating the inverse of the wafer printing model from the wafer printing model.
11. The method of claim 9 , wherein the variation comprises a lateral dimension deviation of two critical dimensions.
12. The method of claim 11 , wherein the critical dimension comprises one or more of a distance between bridges, a via enclosure dimension, and a gate endcap pullback dimension.
13. The method of claim 9 , wherein the difference equation is represented by an expression
|P*P −1 −I|+μ|P*P −1 d−s|,
wherein μ is a weighting variable, d is a lateral dimension of a contour of the predicted wafer contour model, and s is a measured lateral dimension of an actual silicon contour.
14. A method, comprising:
determining a RET process model and a wafer printing process model for a semiconductor fabrication process;
determining, via a computer system, an inverse of the RET process model and combining the inverse of the RET process model with the printing process model to generate a lumped process model, wherein the inverse RET model is an approximate inverse of the wafer printing model;
applying the lumped process model to a circuit to be manufactured using the fabrication process to generate predicted silicon contours for the circuit;
determining a difference of a lateral dimension of the contours predicted silicon contours and an as-designed contour of the circuit design layout, wherein the lateral dimension is parallel to a planar surface of the wafer; and
modifying the circuit design layout to reduce the difference in the lateral dimension.
15. The method of claim 14 , wherein the difference in lateral dimension comprises a lateral dimension deviation of two critical dimensions.
16. The method of claim 15 , wherein the critical dimension comprises a distance between bridges, a via enclosure dimension, or a gate endcap pullback dimension.
17. The method of claim 14 , wherein the determining further comprises minimizing a difference of a hot spots, sensitivity, mask error enhancement-factor, and normalized image log slope between the predicted wafer contour model and the as-designed contour of the circuit design layout.
18. The method of claim 14 , wherein the predicted silicon contour model is represented by an expression
P*P −1 ,
wherein P is the wafer printing model and P −1 is the inverse RET model.
19. The method of claim 18 , wherein the predicted silicon contour model is represented by an expression
|P*P −1 −I|,
wherein I is an identity model representing an as-designed circuit layout.
20. The method of claim 19 , the predicted silicon contour model is represented by an expression
|P*P −1 −I|+μ|P*P −1 d−s|,
wherein μ is a weighting variable, d is a lateral dimension of a contour of the predicted silicon contour model, and s is a measured lateral dimension of an actual silicon contour.