Self-aligned contacts for transistors

1. A method comprising:

patterning an etch-resistant material to create an opening that resides above a transistor gate structure and above areas adjacent to the transistor gate structure, wherein the transistor gate structure comprises a metal transistor gate and spacers adjacent to the metal transistor gate, wherein a top, metal portion of the transistor gate is exposed by the opening;

performing a selective etch through the opening that does not etch the transistor gate structure but does etch material that resides laterally with respect to the transistor gate structure in order to expose tops, immediately adjacent to the transistor gate structure, of drain and source regions of a diffusion layer of the transistor;

depositing conductive material that covers respective tops of the drain and source regions of the diffusion layer of the transistor to a depth that does not short the drain and source regions of the diffusion layer of the transistor;

forming a layer above the conductive material;

forming, through the layer above the conductive material, contacts to respective portions of the conductive material that cover respective tops of the drain and source regions of the diffusion layer of the transistor.

2. The method of claim 1 , wherein the transistor gate structure comprises a plurality of spaced transistor gates with respective adjacent spacers.

3. The method of claim 1 , further comprising forming, through the layer above the conductive material, a contact to the gate of the transistor.

4. The method of claim 1 , further comprising forming metal lines that contact respective tops of the contacts.

5. The method of claim 1 , wherein the transistor is a trigate transistor.

6. The method of claim 1 , wherein the spacers are comprised of silicon nitride.

7. The method of claim 1 , wherein depositing conductive material comprises;

depositing contact metal;

polishing the contact metal until the contact metal is planarized with respect to a top of transistor gate structure.

8. The method of claim 1 , wherein forming contacts to respective portions of the conductive material comprises:

patterning photoresist on the layer above the conductive material;

etching (1) a first via through the layer above the conductive material to a portion of the conductive material that covers the top of the drain region of the diffusion layer of the transistor and (2) a second via through the layer above the conductive material to a portion of the conductive material that covers the top of the source region of the diffusion layer of the transistor;

depositing contact metal within the first and second vias.

9. A method comprising:

polishing a wafer that includes a gate, spacers adjacent to the gate, and a diffusion layer with drain and source regions, wherein the polishing stops at a top of the spacers, wherein a top, conductive portion of the gate is exposed by the polishing;

removing an upper portion of the gate so that a top of the gate is recessed with respect to the top of the spacers such that a gate recess is formed;

filling the gate with a protective material;

patterning an etch-resistant material to create an opening that resides (1) above the spacers, (2) above the protective material, and (3) above areas adjacent to the spacers;

performing a selective etch through the opening that does not etch the gate, the protective material, or the spacers, but does etch material that resides laterally with respect to the spacers in order to expose tops, immediately adjacent to the spacers, of the drain and source regions of the diffusion layer;

depositing conductive material that covers respective tops of the drain and source regions of the diffusion layer to a depth that does not short the drain and source regions of the diffusion layer;

forming a layer above the conductive material;

forming, in the layer above the conductive material, metal lines that contact respective portions of the conductive material that cover respective tops of the drain and source regions of the diffusion layer.

10. The method of claim 9 , wherein the protective material is silicon nitride.

11. The method of claim 9 , further comprising forming a contact to the gate of the transistor.

12. The method of claim 11 , wherein forming a contact to the gate of transistor comprises:

prior to performing a selective etch, removing the protective material from the gate recess and removing partial upper portions of the spacers in order to form a spacer recess;

depositing contact material in the spacer recess;

forming, in the layer above the conductive material, a metal line that contacts the conductive material in the spacer recess.

13. The method of claim 11 , wherein forming a contact to the gate of the transistor comprises:

forming an opening in the layer above the conductive material that exposes a top of the spacers and the protective material filling the gate recess;

removing the protective material from the gate recess and removing partial upper portions of the spacers in order to form a spacer recess;

depositing contact material in the spacer recess;

filling the opening in the layer above the conductive material with a metal line that contacts the contact material in the spacer recess.

14. The method of claim 9 , wherein the transistor is a trigate transistor.

15. The method of claim 9 , wherein the transistor gate is comprised of metal and the spacers are comprised of silicon nitride.

16. The method of claim 9 , wherein depositing conductive material comprises:

depositing contact metal;

polishing the contact metal until the contact metal is planarized with respect to a top of the spacers.

17. The method of claim 9 , wherein forming metal lines comprises:

patterning photoresist on the layer above the conductive material;

etching a first opening in the layer above conductive material that exposes a top of the conductive material that covers the top of the drain region of the diffusion layer of the transistor;

etching a second opening in the layer above the conductive material that exposes a top of the conductive material that covers the top of the source region of the diffusion layer of the transistor;

depositing metal lines within the first and second openings.