System for predictive processor component suspension and method thereof
View Patent ↗An instruction cycle is determined from instructions stored in a cache, where the instruction cycle represents the sequence of instructions predicted to be executed by the processing device that are resident in the cache. The duration of the instruction cycle is estimated and one or more components of the processing device that are not expected to be used during the instruction cycle may be suspended for a portion or all of the duration. The components may be suspended by, for example, clock gating or by isolating the components from one or more power domains.
1. A method comprising:
receiving a plurality of instructions;
identifying one or more components of a processor that are expected to be unused during an execution of a sequence of instructions from the plurality of instructions; and
selectively suspending at least one of the one or more identified components of the processor during an execution of at least a portion of the sequence of instructions by the processor based on an amount of power expected to be consumed to reenable the at least one component.
2. The method of claim 1 , wherein suspending the at least one component includes isolating the at least one component from one or more power domains.
3. The method of claim 1 , wherein suspending the at least one component includes clock gating the at least one component.
4. The method of claim 1 , wherein selectively suspending the at least one component comprises:
suspending the at least one component in response to determining an amount of power expected to be consumed by maintaining the at least one component in an enabled state for the execution of at least a portion of the sequence of instructions is not less than the amount of power expected to be consumed to reenable the at least one component; and
maintaining the at least one component in an enabled state in response to determining the amount of power expected to be consumed by maintaining the at least one component in an enabled state for the execution of at least a portion of the sequence of instructions is not greater than the amount of power expected to be consumed to reenable the at least one component.
5. A method comprising:
storing a plurality of instructions in a cache of a processor;
identifying one or more components of the processor expected to be unused during an execution of a sequence of instructions of the plurality of instructions by the processor;
estimating, at the processor, a duration before an instruction not in the sequence of instructions is to be requested for execution by the processor; and
suspending, based on the duration, at least one of the one or more identified components of the processor during an execution of at least a portion of the sequence of instructions by the processor.
6. The method of claim 5 , wherein the at least one component is suspended when a power consumption associated with suspending and reenabling the at least one component is less than a power consumption associated with maintaining the at least one component in an enabled state for the duration.
7. The method of claim 6 , wherein the at least one component is suspended by clock gating the at least one component when the duration is greater than a first threshold.
8. The method of claim 7 , wherein suspending the at least one component includes isolating the at least one component from one or more power domains when the duration is greater than a second threshold, and wherein the second threshold is greater than the first threshold.
9. The method of claim 6 , wherein suspending the at least one component includes isolating the at least one component from one or more power domains when the number of cycles is greater than a first threshold.
10. A processor comprising:
a plurality of components;
storage means for storing a plurality of instructions;
means for identifying one or more components of the plurality of components that are expected to be unused during an execution of a sequence of instructions of the plurality of instructions by the processor; and
means for selectively suspending at least one of the one or more identified components during an execution of at least a portion of the sequence of instructions by the processor based on an amount of power expected to be consumed to reenable the at least one component.
11. The processor of claim 10 , wherein the means for suspending the at least one component includes means for clock gating the at least one component.
12. The processor of claim 10 , wherein the means for suspending the at least one component includes means for isolating the at least one component from one or more power domains.
13. The processor of claim 10 , further comprising means for determining a duration before an instruction not included in the sequence of instructions is to be requested for execution by the processor.
14. The processor of claim 13 , wherein the means for selectively suspending the at least one component includes means for clock gating the at least one component when the duration is greater than a first threshold.
15. The processor of claim 13 , wherein the means for selectively suspending the at least one component includes means for isolating the at least one component from one or more power domains when the duration is greater than a second threshold, where the second threshold is greater than the first threshold.
16. The processor of claim 13 , wherein the means for selectively suspending the at least one component includes means for isolating the at least one component from one or more power domains when the duration is greater than a first threshold.
17. The processor of claim 10 , wherein the means for selectively suspending the at least one component comprises:
means for suspending the at least one component in response to determining an amount of power expected to be consumed by maintaining the at least one component in an enabled state for the execution of at least a portion of the sequence of instructions is not less than the amount of power expected to be consumed to reenable the at least one component; and
means for maintaining the at least one component in an enabled state in response to determining the amount of power expected to be consumed by maintaining the at least one component in an enabled state for the execution of at least a portion of the sequence of instructions is not greater than the amount of power expected to be consumed to reenable the at least one component.
18. A processor comprising:
a plurality of components;
a decode cache to store a plurality of instructions to be executed by the processor; and
a controller to:
identify one or more of the plurality of components expected to be unused during an execution of a sequence of instructions of the plurality of instructions by the processor;
determine a duration before an instruction not included in the sequence of instructions is to be requested for execution by the processor; and
initiate a suspension of at least one of the one or more components for at least a portion of the execution of the sequence of instructions by the processor based on the duration.
19. The processor of claim 18 , wherein the controller initiates the suspension of the at least one component by initiating a clock gating of the one or more components.
20. The processor of claim 18 , wherein the controller initiates the suspension of the at least one component by initiating an isolation of the one or more components from one or more power domains.
21. The processor of claim 18 , wherein the controller initiates the suspension of the one or more components by initiating a clock gating of the one or more components when the duration is greater than a first threshold, and wherein the controller initiates the suspension of the one or more components by initiating an isolation of the one or more components from one or more power domains when the duration is greater than a second threshold, where the second threshold is greater than the first threshold.