Phase change memory cell defined by a pattern shrink material process

1. A method for fabricating a memory cell device, the method comprising:

providing a preprocessed wafer having a first electrode;

depositing an isolation material layer adjacent the preprocessed wafer;

applying photoresist adjacent the isolation material layer;

patterning an opening having a first width in the photoresist;

applying a pattern shrink material layer over the photoresist and the opening;

reducing the first width to a second width while maintaining a shape of sidewalls of the opening using the pattern shrink material layer;

removing the pattern shrink material layer;

etching the isolation material layer to expose the first electrode;

removing the photoresist;

depositing phase-change material in the opening; and

fabricating a second electrode adjacent the phase-change material.

2. A method for fabricating a memory cell device, the method comprising:

providing a preprocessed wafer having a first electrode;

depositing an isolation material layer adjacent the preprocessed wafer;

applying photoresist adjacent the isolation material layer;

patterning an opening having a first width in the photoresist;

applying a first pattern shrink material layer over the photoresist and the opening;

baking to reduce the first width to a second width;

removing the first pattern shrink material layer;

etching the isolation material layer to expose the first electrode;

removing the photoresist;

depositing phase-change material in the opening; and

fabricating a second electrode adjacent the phase-change material.

3. The method of claim 2 , further comprising:

applying a second pattern shrink material layer over the photoresist and the opening;

baking to reduce the second width to a third width; and

removing the second pattern shrink material layer.

4. The method of claim 2 , wherein applying the first pattern shrink material layer comprises applying a SAFIER™ material layer.

5. The method of claim 4 , wherein baking comprises baking the SAFIER™ material layer to shrink the SAFIER™ material and flow the photoresist.

6. The method of claim 2 , wherein applying the first pattern shrink material layer comprises applying a RELACS™ material layer.

7. The method of claim 6 , wherein baking comprises baking the RELACS™ material layer to form a compound layer with the photoresist.

8. The method of claim 2 , wherein depositing the phase-change material comprises depositing a chalcogenide.

9. The method of claim 2 , wherein providing the preprocessed wafer comprises providing a preprocessed wafer comprising one of a tungsten plug and a copper plug.

10. The method of claim 2 , wherein patterning the opening comprises patterning a cylindrical opening.

11. The method of claim 2 , wherein patterning the opening comprises patterning a trench opening.

12. A method for fabricating a memory cell device, the method comprising:

providing a preprocessed wafer having a first electrode;

depositing an isolation material layer adjacent the preprocessed wafer;

applying photoresist adjacent the isolation material layer;

patterning an opening having a first width in the photoresist;

applying a pattern shrink material layer over the photoresist and the opening;

reducing the first width to a second width while maintaining a shape of sidewalls of the opening using the pattern shrink material layer;

removing the pattern shrink material layer;

etching the isolation material layer to expose the first electrode;

removing the photoresist;

depositing heater material in the opening;

depositing a phase-change material layer adjacent the heater material;

depositing an electrode material layer adjacent the phase-change material layer; and

etching the electrode material layer and the phase-change material layer to form a second electrode and a memory storage location.

13. A method for fabricating a memory cell device, the method comprising:

providing a preprocessed wafer having a first electrode;

depositing an isolation material layer adjacent the preprocessed wafer;

applying photoresist adjacent the isolation material layer;

patterning an opening having a first width in the photoresist;

applying a first pattern shrink material layer over the photoresist and the opening;

baking to reduce the first width to a second width;

removing the first pattern shrink material layer;

etching the isolation material layer to expose the first electrode;

removing the photoresist;

depositing heater material in the opening;

depositing a phase-change material layer adjacent the heater material;

depositing an electrode material layer adjacent the phase-change material layer; and

etching the electrode material layer and the phase-change material layer to form a second electrode and a memory storage location.

14. The method of claim 13 , further comprising

applying a second pattern shrink material layer over the photoresist and the opening;

baking to reduce the second width to a third width; and

removing the second pattern shrink material layer.

15. The method of claim 13 , wherein applying the first pattern shrink material layer comprises applying a SAFIER™ material layer.

16. The method of claim 15 , wherein baking comprises baking the SAFIER™ material layer to shrink the SAFIER material and flow the photoresist.

17. The method of claim 13 , wherein applying the first pattern shrink material layer comprises applying a RELACS™ material layer.

18. The method of claim 17 , wherein baking comprises baking the RELACS™ material layer to form a compound layer with the photoresist.

19. The method of claim 13 , wherein depositing the phase-change material comprises depositing a chalcogenide.

20. The method of claim 13 , wherein providing the preprocessed wafer comprises providing a preprocessed wafer comprising one of a tungsten plug and a copper plug.

21. The method of claim 13 , wherein patterning the opening comprises patterning a cylindrical opening.

22. The method of claim 13 , wherein patterning the opening comprises patterning a trench opening.

23. A method for fabricating a memory cell device, the method comprising:

providing a preprocessed wafer having a first electrode;

depositing an isolation material layer adjacent the preprocessed wafer;

applying photoresist adjacent the isolation material layer;

patterning an opening having a first width in the photoresist;

applying a SAFIER™ material layer over the photoresist and the opening;

baking the SAFIER material layer to shrink the SAFIER material and flow the photoresist;

removing the SAFIER material layer to provide the opening having a second width less than the first width;

etching the isolation material layer to expose the first electrode;

removing the photoresist;

depositing phase-change material in the opening; and

fabricating a second electrode adjacent the phase-change material.

24. The method of claim 23 , wherein depositing the phase-change material comprises depositing a chalcogenide.

25. The method of claim 23 , wherein patterning the opening comprises patterning a cylindrical opening.

26. The method of claim 23 , wherein patterning the opening comprises patterning a trench opening.

27. A method for fabricating a memory cell device, the method comprising:

providing a preprocessed wafer having a first electrode;

depositing an isolation material layer adjacent the preprocessed wafer;

applying photoresist adjacent the isolation material layer;

patterning an opening having a first width in the photoresist;

applying a RELACS™ material layer over the photoresist and the opening;

baking the RELACS material layer to form a compound layer with the photoresist;

removing the RELACS material layer without removing the compound layer to provide the opening having a second width less than the first width;

etching the isolation material layer to expose the first electrode;

removing the compound layer and the photoresist;

depositing phase-change material in the opening; and

fabricating a second electrode adjacent the phase-change material.

28. The method of claim 27 , wherein depositing the phase-change material comprises depositing a chalcogenide.

29. The method of claim 27 , wherein patterning the opening comprises patterning a cylindrical opening.

30. The method of claim 27 , wherein patterning the opening comprises patterning a trench opening.

31. A method for fabricating a memory cell device, the method comprising:

providing a preprocessed wafer having a first electrode;

depositing an isolation material layer adjacent the preprocessed wafer;

applying photoresist adjacent the isolation material layer;

patterning an opening having a first width in the photoresist;

applying a SAFIER™ material layer over the photoresist and the opening;

baking the SAFIER material layer to shrink the SAFIER material and flow the photoresist;

removing the SAFIER material layer to provide the opening having a second width less than the first width;

etching the isolation material layer to expose the first electrode;

removing the photoresist;

depositing heater material in the opening;

depositing a phase-change material layer adjacent the heater material;

depositing an electrode material layer adjacent the phase-change material layer; and

etching the electrode material layer and the phase-change material layer to form a second electrode and a memory storage location.

32. The method of claim 31 , wherein depositing the phase-change material layer comprises depositing a chalcogenide material layer.

33. The method of claim 31 , wherein patterning the opening comprises patterning a cylindrical opening.

34. The method of claim 31 , wherein patterning the opening comprises patterning a trench opening.

35. A method for fabricating a memory cell device, the method comprising:

providing a preprocessed wafer having a first electrode;

depositing an isolation material layer adjacent the preprocessed wafer;

applying photoresist adjacent the isolation material layer;

patterning an opening having a first width in the photoresist;

applying a RELACS™ material layer over the photoresist and the opening;

baking the RELACS material layer to form a compound layer with the photoresist;

removing the RELACS material layer without removing the compound layer to provide the opening having a second width less than the first width;

etching the isolation material layer to expose the first electrode;

removing the compound layer and the photoresist;

depositing heater material in the opening;

depositing a phase-change material layer adjacent the heater material;

depositing an electrode material layer adjacent the phase-change material layer; and

etching the electrode material layer and the phase-change material layer to form a second electrode and a memory storage location.

36. The method of claim 35 , wherein depositing the phase-change material layer comprises depositing a chalcogenide material layer.

37. The method of claim 35 , wherein patterning the opening comprises patterning a cylindrical opening.

38. The method of claim 35 , wherein patterning the opening comprises patterning a trench opening.