Internal voltage generation control circuit and internal voltage generation circuit using the same
View Patent ↗An internal voltage generation control circuit and an internal voltage generation circuit using the same are provided. The internal voltage generation control circuit comprises first to n-th latches and a logic unit. The first latch receives, as an input signal, a column active pulse signal generated after a read/write command is input, and latches state information of the column active pulse signal, received when a clock signal is enabled, during a predetermined time, and then outputs the latched information. A k-th latch (2≦k≦n) receives an output signal of a k−1-th latch, and latches state information of the output signal of the k−1-th latch, received when the clock signal is enabled, during a predetermined time, and then outputs the latched information. The logic unit performs a logical operation between the column active pulse signal and output signals of the n latches and outputs an internal voltage generation control signal.
1. An internal voltage generation control circuit comprising:
a first latch for receiving, as an input signal, a column active pulse signal that is generated after a read or write command is input, and latching state information of the column active pulse signal, which is received when a clock signal is enabled, during a predetermined time, and then outputting the latched state information;
second to n-th latches, wherein a k-th latch receives, as an input signal, an output signal of a k−1-th latch, and latches state information of the output signal of the k−1-th latch, which is received when the clock signal is enabled, during a predetermined time, and then outputs the latched state information, where k and n are natural numbers satisfying 2≦k≦n; and
a logic unit for performing a logical operation between the column active pulse signal and output signals of the first to n-th latches and outputting an internal voltage generation control signal.
2. The internal voltage generation control circuit according to claim 1 , wherein each of the first to n-th latches latches state information of an input signal received at a falling edge of the clock signal and outputs the latched state information in synchronization with a next rising edge of the clock signal.
3. The internal voltage generation control circuit according to claim 1 , wherein each of the first to n-th latches latches state information of an input signal received at a rising edge of the clock signal and outputs the latched state information in synchronization with a next falling edge of the clock signal.
4. The internal voltage generation control circuit according to claim 2 or 3 , wherein each of the first to n-th latches includes a flip-flop.
5. The internal voltage generation control circuit according to claim 2 or 3 , wherein each of the first to n-th latches includes a shift register.
6. The internal voltage generation control circuit according to claim 1 , wherein the natural number “n” is greater than or equal to the number of clock periods including at least a latency and a burst length.
7. The internal voltage generation control circuit according to claim 1 , wherein the logic unit performs an OR operation between the column active pulse signal and output signals of the first to n-th latches and outputs a signal indicating a result of the OR operation.
8. An internal voltage generation circuit comprising:
a row active control unit for outputting a first internal voltage generation control signal that is enabled after an active command is input and is then disabled after at least a Row Address Strobe (RAS) activation time elapses;
a column active control unit for outputting a second internal voltage generation control signal that remains enabled during a time interval corresponding to clock periods including at least a latency and a burst length after being enabled in synchronization with input of a read or write command;
a row precharge control unit for outputting a third internal voltage control signal that is enabled after a row precharge command is input and is then disabled after a predetermined delay time elapses;
a first logic unit for performing a logical operation between the first to third internal voltage generation control signals and outputting a signal indicating a result of the logical operation; and
an internal voltage generator for generating an internal voltage in response to the signal output from the first logic unit.
9. The internal voltage generation circuit according to claim 8 , wherein the column active control unit comprises:
a first latch for receiving, as an input signal, a column active pulse signal that is generated after the read or write command is input, and latching state information of the column active pulse signal, which is received when a clock signal is enabled, during a predetermined time, and then outputting the latched state information;
second to n-th latches, wherein a k-th latch receives, as an input signal, an output signal of a k−1-th latch, and latches state information of the output signal of the k−1-th latch, which is received when the clock signal is enabled, during a predetermined time, and then outputs the latched state information, where k and n are natural numbers satisfying 2≦k≦n; and
a second logic unit for performing a logical operation between the column active pulse signal and output signals of the first to n-th latches and outputting the second internal voltage generation control signal.
10. The internal voltage generation circuit according to claim 9 , wherein each of the first to n-th latches latches state information of an input signal received at a falling edge of the clock signal and outputs the latched state information in synchronization with a next rising edge of the clock signal.
11. The internal voltage generation circuit according to claim 9 , wherein each of the first to n-th latches latches state information of an input signal received at a rising edge of the clock signal and outputs the latched state information in synchronization with a next falling edge of the clock signal.
12. The internal voltage generation circuit according to claim 10 , wherein each of the first to n-th latches includes a flip-flop.
13. The internal voltage generation circuit according to claim 10 , wherein each of the first to n-th latches includes a shift register.
14. The internal voltage generation circuit according to claim 9 , wherein the natural number “n” is greater than or equal to the number of clock periods including at least a latency and a burst length.
15. The internal voltage generation circuit according to claim 9 , wherein the second logic unit performs an OR operation between the column active pulse signal and output signals of the first to n-th latches and outputs a signal indicating a result of the OR operation.
16. The internal voltage generation circuit according to claim 8 , wherein the first logic unit performs an OR operation between the first to third internal voltage generation control signals and outputs a signal indicating a result of the logical operation.