Compact and hitlessly-resizable multi-channel queue
A queue is disclosed (i) that provides for single-channel and multi-channel operation and that can change between single-channel and multi-channel operation during operation hitlessly, (ii) in which the number of channels and each channel's size can be changed during operation hitlessly, and (iii) is compact. To accomplish this, the illustrative embodiment comprises a group of doubly-linked lists, one for each channel's storage. One set of links indicates the node where the next datum is to be written and the other set of links indicates the node where the next datum is to be read. By bifurcating each channel's queue into a set of write links and read links, the illustrative embodiment can resize a channel during operation hitlessly.
1 . A system comprising:
a first memory comprising 2 N individually-addressable words;
a second memory comprising 2 M individually-addressable M-bit words, wherein each of said M-bit words is (1) a pointer into said second memory and (2) at least a portion of a pointer into said first memory; and
a third memory comprising 2 M individually-addressable M-bit words, wherein each of said M-bit words is (1) a pointer into said third memory and (2) at least a portion of a pointer into said first memory;
wherein M and N are positive integers and N≧M.
2 . The system of claim 1 wherein second memory comprises a plurality of linked-lists and said third memory comprises a plurality of linked-lists.
3 . The system of claim 1 further comprising:
a write-pointer memory comprising B individually-addressable N-bit words, wherein each of said N-bit words is a pointer into said first memory, and wherein M bits of each of said N-bit words is a pointer into said second memory; and
a read-pointer memory comprising B individually-addressable N-bit words, wherein each of said N-bit words is a pointer into said first memory, and wherein M bits of each of said N-bit words is a pointer into said third memory;
wherein B is a positive integer.
4 . A method comprising:
reading an M-bit pointer from a first memory that comprises 2 M individually-addressable M-bit words;
writing a word to a second memory using said M-bit pointer as a portion of said address;
writing said M-bit pointer to a third memory that comprises 2 M individually-addressable M-bit words;
reading said M-bit pointer from said third memory; and
reading said word from said second memory using said M-bit pointer as a portion of said address.
5 . The method of claim 4 wherein said M-bit pointer is a link in a linked list.
6 . A method comprising:
reading a first N-bit pointer from a first memory that comprises B individually-addressable N-bit words using B as the address;
writing a word to a second memory that comprises 2 N individually-addressable words using said first N-pointer as the address;
reading a first M-bit pointer from a third memory that comprises 2 M individually-addressable M-bit words using said at least a portion of said first N-bit pointer as the address; and
writing said first M-bit pointer into said first memory using B as the address.
7 . The method of claim 6 wherein said M-bit pointer is a link in a linked list.
8 . The method of claim 6 further comprising:
reading a second N-bit pointer from a fourth memory that comprises B individually-addressable N-bit words using B as the address;
writing said word from said second memory using said second N-bit pointer as the address;
reading a second M-bit pointer from a fifth memory that comprises 2 M individually-addressable M-bit words using said at least a portion of said second N-bit pointer as the address; and
writing said first M-bit pointer into said fifth memory using B as the address.