Method for manufacturing a transistor
View Patent ↗A semiconductor device and a method for manufacturing the same is disclosed, in which a spacer containing nitrogen therein has a tensile stress and enables device reliability improvement by improving the On-current without regard to the kind of transistor. The semiconductor device includes a semiconductor substrate; a gate insulating layer and a gate electrode on the semiconductor substrate; spacers at sidewalls of the gate electrode, wherein the spacer contains nitrogen to obtain or increase its tensile stress; and source and drain regions in the semiconductor substrate adjacent to the gate electrode.
1. A method for manufacturing a semiconductor device comprising:
forming a gate electrode on a semiconductor substrate;
forming a first insulating layer on the semiconductor substrate including the gate electrode;
forming a second insulating layer on the first insulating layer by introducing TEOS and a nitrogen source gas into a low pressure chemical vapor deposition chamber, wherein the second insulating layer contains nitrogen therein and has a tensile stress; and
forming spacers at sidewalls of the gate electrode by anisotropically etching the first and second insulating layers.
2. The method of claim 1 , further comprising forming a buffer layer on the semiconductor substrate before forming the first insulating layer.
3. The method of claim 2 , wherein the buffer layer has a thickness between 100 Å and 200 Å, the first insulating layer has a thickness between 100 Å and 200 Å, and the second insulating layer has a thickness between 500 Å and 1000 Å.
4. The method of claim 1 , further comprising:
forming lightly doped regions in the semiconductor substrate, adjacent to the gate electrode; and
forming source and drain regions adjacent to the spacers by implanting a high dose or concentration of impurity ions into the substrate, using the gate electrode and the spacers as a mask.
5. The method of claim 4 , further comprising forming a suicide layer on the gate electrode, the source region and the drain region.
6. A method for manufacturing a semiconductor device comprising:
forming a buffer oxide layer on a semiconductor substrate before forming a first insulating layer;
forming the first insulating layer on the semiconductor substrate and a gate electrode, wherein the first insulating layer comprises silicon nitride;
forming a second insulating layer on the first insulating layer, wherein the second insulating layer contains sufficient nitrogen to increase a tensile stress and improve an on-current of the semiconductor device, and wherein the second insulating layer comprises an oxynitride; and
forming spacers at sidewalls of the gate electrode by anisotropically etching the first and second insulating layers.
7. The method of claim 6 , wherein the step of forming the second insulating layer includes:
depositing an insulating material on the first insulating layer;
implanting nitrogen ions to the insulating material; and
performing a thermal process to activate the nitrogen ions.
8. The method of claim 7 , wherein the thermal process is performed at a temperature between 700° C. and 800° C. for 8 to 12 seconds in a rapid thermal anneal (RTA) apparatus.
9. The method of claim 6 , wherein the second insulating layer comprises a TEOS oxide layer.
10. The method of claim 6 , wherein the buffer layer has a thickness between 100 Å and 200 Å and the first insulating layer has a thickness between 100 Å and 200 Å.
11. The method of claim 10 , wherein the second insulating layer has a thickness between 500 Å and 1000 Å.
12. The method of claim 6 , wherein the step of forming the second insulating layer comprises introducing TEOS into a low pressure chemical vapor deposition chamber.
13. The method of claim 6 , further comprising:
forming lightly doped regions in the semiconductor substrate, adjacent to the gate electrode; and
forming source and drain regions adjacent to the spacers by implanting a high dose or concentration of impurity ions into the substrate, using the gate electrode and the spacers as a mask.
14. The method of claim 13 , further comprising forming a silicide layer on the gate electrode, the source region and the drain region.
15. A method for manufacturing a semiconductor device comprising:
forming a gate electrode on a semiconductor substrate;
forming a first insulating layer on the semiconductor substrate including the gate electrode;
forming a second insulating layer on the first insulating layer, wherein the second insulating layer contains nitrogen therein, has a tensile stress, and comprises a TEOS oxide layer; and
forming spacers at sidewalk of the gate electrode by anisotropically etching the first and second insulating layers.
16. The method of claim 15 , further comprising forming a buffer layer on the semiconductor substrate before forming the first insulating layer.
17. The method of claim 16 , wherein the buffer layer has a thickness between 100 Å and 200 Å, the first insulating layer has a thickness between 100 Å and 200 Å, and the second insulating layer has a thickness between 500 Å and 1000 Å.
18. The method of claim 15 , wherein the step of forming the second insulating layer comprises introducing TEOS and a nitrogen source gas into a low pressure chemical vapor deposition chamber.
19. The method of claim 15 , wherein the step of forming the second insulating layer includes:
implanting nitrogen ions to the TEOS oxide; and
performing a thermal process to activate the nitrogen ions.
20. The method of claim 19 , wherein the thermal process is performed at a temperature between 700° C. and 800° C. for 8 to 12 seconds in a rapid thermal anneal (RTA) apparatus.