Memory device capable of detecting its failure
View Patent ↗A memory device capable of detecting its failure, the memory device includes a data input section for receiving data applied from an external part of the memory device; a latch section for receiving and storing therein the data which have passed through the data input section; memory cell arrays for storing therein the data which have passed through the data input section; and a data compressor for determining whether or not the data stored in the latch section and the data stored in the memory cell arrays are identical to each other.
1. A memory device capable of detecting its failure, the memory device comprising:
a data input section for receiving data applied from an external part of the memory device;
a latch section for receiving and storing therein the data which have passed through the data input section, wherein output data of the latch section are compressed data produced by compressing output data of the data input section;
memory cell arrays for storing therein the data which have passed through the data input section, wherein output data of the memory cell arrays are uncompressed data; and
a data compressor for determining whether or not the data stored in the latch section and the data stored in the memory cell arrays are identical to each other.
2. The memory device capable of detecting its failure as claimed in claim 1 , wherein the memory device further comprises a data output section for receiving output signals of the data compressor, and it is possible to determine whether or not the data stored in the latch section and the data stored in the memory cell arrays are identical to each other, based on logic signal values output from the data output section.
3. The memory device capable of detecting its failure as claimed in claim 1 , wherein the memory device further comprises a data output section for receiving output signals of the data compressor, and an output terminal of the data output section is connected to data pads of the memory device.
4. The memory device capable of detecting its failure as claimed in claim 1 , wherein the data compressor comprises:
a first comparator for determining whether or not logic values of the data stored in the memory cell arrays are all identical;
a second comparator for determining whether or not the data stored in the memory cell arrays and the data stored in the latch section are all identical; and
a third comparator for determining whether or not the determination result of the first comparator and the determination result of the second comparator are identical to each other.
5. A memory device capable of detecting its failure, the memory device comprising:
a data input section for receiving data applied from an external part of the memory device, classifying the received data into N even data groups and N odd data groups and outputting the classified data groups, wherein the N is a natural number;
a latch section for storing first data of each of said N even data groups and said N odd data groups therein, wherein output data of the latch section are compressed data produced by compressing output data of the data input section;
memory cell arrays for storing the N even data groups and the N odd data groups therein, wherein output data of the memory cell arrays are uncompressed data; and
a data compressor for determining whether or not first logic levels and second logic levels are identical, wherein the first logic levels are the logic levels of the first data of each data group stored in the latch section, and the second logic levels are the logic levels of both the N even data groups and the N odd data groups stored in the memory cell arrays corresponding to said data groups, respectively.
6. The memory device capable of detecting its failure as claimed in claim 5 , wherein the data compressor comprises:
a first comparator for determining whether or not logic values of the data groups stored in the memory cell arrays are identical;
a second comparator for determining whether or not third logic levels and fourth logic levels are identical, wherein the third logic levels are the logic levels of the first data of each data group stored in the memory cell arrays, and the fourth logic levels are the logic levels of the first data of each data group stored in the latch section, wherein each data group stored in the latch section corresponds to said each data group stored in the memory cell arrays; and
a third comparator for determining whether or not the determination result of the first comparator and the determination result of the second comparator are identical to each other.