High voltage switching circuit of a NAND type flash memory device
View Patent ↗A high voltage switching circuit of a NAND type flash memory device that includes a clock level shifter for increasing an amplitude of a clock signal, a pass voltage generator for outputting a pass voltage by pumping a power source voltage in response to a clock signal with an increased amplitude, and a high voltage pass transistor for transferring a high voltage according to the pass voltage.
1. A high voltage switching circuit of a NAND type flash memory device, the high voltage switching circuit comprising:
a clock level shifter for increasing an amplitude of a clock signal, wherein the clock level shifter comprises:
precharging means connected to a power source voltage terminal and configured to precharge first and second nodes;
a first capacitor connected between the first node and an input terminal of the clock signal, for increasing a voltage of the first node in response to the clock signal;
a second capacitor connected between the second node and an input terminal of an inversed clock signal, for increasing a voltage of the second node in response to the inversed clock signal;
a first switching element connected between the first node and a first output terminal, for transferring an increased voltage of the first node to the first output terminal;
a second switching element connected between the second node and a second output terminal, for transferring an increased voltage of the second node to the second output terminal;
a first discharging element for discharging the first output terminal in response to the inversed clock signal; and
a second discharging element for discharging the second output terminal in response to the clock signal;
a pass voltage generator for outputting a pass voltage by pumping an external high voltage(Vpp) in response to a clock signal with an increased amplitude; and
a high voltage pass transistor for transferring an input high voltage(HVIN) according to the pass voltage.
2. The high voltage switching circuit as set forth in claim 1 , wherein the precharging means comprises:
first means for precharging the first node; and
second means for precharging the second node.
3. The high voltage switching circuit as set forth in claim 2 , wherein the first means for precharging the first node comprises:
a transistor connected between the power source voltage terminal and the first node, the transistor being operable in accordance with a potential of the second node; and
a diode connected between the power source voltage terminal and the first node.
4. The high voltage switching circuit as set forth in claim 2 , wherein the second means for precharging the second diode comprises:
a transistor connected between the power source voltage terminal and the second node, the transistor being operable in accordance with a potential of the first node; and
a diode connected between the power source voltage terminal and the second node.
5. The high voltage switching circuit as set forth in claim 3 , wherein the transistor is formed of an NMOS transistor.
6. The high voltage switching circuit as set forth in claim 3 , wherein the diode is formed of an NMOS transistor whose gate is connected to the power source voltage terminal.
7. The high voltage switching circuit as set forth in claim 1 , further comprising:
a first delay circuit connected between the clock signal input terminal and the first capacitor, for delaying the clock signal; and
a second delay circuit connected between the clock signal input terminal and the second capacitor, for delaying the inversed clock signal.
8. The high voltage switching circuit as set forth in claim 1 , wherein the first or second switching element is formed of a PMOS transistor whose gate is coupled to the power source voltage.
9. The high voltage switching circuit as set forth in claim 1 , wherein the first or second discharging element is formed of an NMOS transistor.
10. The high voltage switching circuit as set forth in claim 1 , wherein the pass voltage generator comprises:
an input circuit for buffering an internal switching enable signal(ENi) and transferring the buffered signal to a pass node, which is connected to a gate of the high voltage pass transistor;
a first capacitor connected to the pass node, for conducting a pumping operation in response to the clock signal with an increased amplitude;
a diode connected between the pass node and an external high voltage(Vpp) terminal, for preventing the pass node from excessively boosting;
a first NMOS transistor connected to the external high voltage(Vpp) terminal, for transferring a voltage of the pass node that is transferred through the diode in accordance with a potential of the pass node;
a second NMOS transistor with a gate connected to the first NMOS transistor, the second NMOS transistor being connected between the pass node and the first NMOS transistor; and
a second capacitor connected to a gate of the second NMOS transistor, for conducting a pumping operation in response to an inversed one of the clock signal with an increased amplitude.
11. A high voltage switching circuit comprising:
a clock level shifter for increasing amplitude of a clock signal, wherein the clock level shifter comprises:
precharging means connected to a power source voltage terminal and configured to precharge first and second nodes;
a first capacitor connected between the first node and an input terminal of the clock signal, for increasing a voltage of the first node in response to the clock signal;
a second capacitor connected between the second node and an input terminal of an inversed clock signal, for increasing a voltage of the second node in response to the inversed clock signal;
a first switching element connected between the first node and a first output terminal, for transferring an increased voltage of the first node to the first output terminal;
a second switching element connected between the second node and a second output terminal, for transferring an increased voltage of the second node to the second output terminal;
a first discharging element for discharging the first output terminal in response to the inversed clock signal; and
a second discharging element for discharging the second output terminal in response to the clock signal.
12. The high voltage switching circuit as set forth in claim 11 , wherein the precharging means comprises:
first means precharging the first node; and
second means precharging the second node.
13. The high voltage switching circuit as set forth in claim 12 , wherein the first means comprises:
a transistor connected between the power source voltage terminal and the first node, being operable in accordance with a potential of the second node; and
a diode connected between the power source voltage terminal and the first node.
14. The high voltage switching circuit as set forth in claim 12 , wherein the second means comprises:
a transistor connected between the power source voltage terminal and the second node, being operable in accordance with a potential of the first node; and
a diode connected between the power source voltage terminal and the second node.
15. The high voltage switching circuit as set forth in one of claim 13 , wherein the transistor is formed of an NMOS transistor.
16. The high voltage switching circuit as set forth in one of claim 13 , wherein the diode is formed of an NMOS transistor whose gate is connected to the power source voltage terminal.
17. The high voltage switching circuit as set forth in claim 11 , which further comprises:
a first delay circuit connected between the input terminal of the clock signal and the first capacitor, delaying the clock signal; and
a second delay circuit connected between the input terminal of the clock signal and the second capacitor, delaying the inversed clock signal.
18. The high voltage switching circuit as set forth in claim 11 , wherein the first or second switching element is formed of a PMOS transistor whose gate is coupled to the power source voltage.
19. The high voltage switching circuit as set forth in claim 11 , wherein the first or second discharging element is formed of an NMOS transistor.
20. The high voltage switching circuit as set forth in claim 11 , further comprising:
a pass voltage generator for outputting a pass voltage by pumping an external high voltage(Vpp) in response to the clock signal of which amplitude is increased by the clock level shifter; and a high voltage pass transistor for transferring an input high voltage(HVIN) according to the pass voltage.
21. The high voltage switching circuit as set forth in claim 20 , wherein the pass voltage generator comprises:
an input circuit for buffering an internal switching enable signal(ENi) and transferring the buffered signal to a pass node, which is connected to a gate of the high voltage pass transistor;
a first capacitor connected to the pass node, conducting a pumping operation in response to the amplitude enlarged clock signal;
a diode connected between the pass node and an external high voltage(Vpp) terminal, preventing the pass node from excessively boosting;
a first NMOS transistor connected to the external high voltage(Vpp) terminal, transferring a voltage of the pass node that is transferred through the diode in accordance with a potential of the pass node;
a second NMOS transistor with a gate connected to the first NMOS transistor, being connected between the pass node and the first NMOS transistor; and
a second capacitor connected to a gate of the second NMOS transistor, conducting a pumping operation in response to an inversed one of the amplitude enlarged clock signal.