IP Library Granted Patent US 7,329,585
Granted Patent B2
US 7,329,585 · App. 11/132,857 · Granted Feb 12, 2008

Method of manufacturing semiconductor device

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Quick Facts
Patent No.
US 7,329,585
App. No.
11/132,857
Granted
Feb 12, 2008
Kind
B2
Abstract

Disclosed herein is a method of manufacturing a semiconductor device, and more specifically, to a method of manufacturing a semiconductor device having a capacitor and a resistor in which a thin film resistor and a capacitor are formed at the same time, a thin film resistor is formed on a metal wiring, and the two thin film resistors are then serially connected. Accordingly, resistance per unit area in substrate can be increased, a device characteristic can be improved and a process unit price can be lowered.

Claims (12)

1. A method of manufacturing a semiconductor device, comprising:

(a) simultaneously forming a capacitor and a first resistor on a semiconductor substrate, by:

(a-1) sequentially depositing a metal film, a barrier film, a dielectric film, a conductive material film, and an etch-stop layer;

(a-2) selectively patterning the etch-stop layer, the conductive material film and the dielectric film to form a capacitor pattern and a first resistor pattern; and

(a-3) selectively patterning the barrier film and the metal film by a photolithography process and an etch process, thus forming a metal wiring;

(b) forming a first interlayer insulating film on the semiconductor substrate in which the capacitor and the first resistor are formed;

(c) forming a plurality of first via plugs that are electrically connected to the capacitor and the resistor, and a first metal wiring that is electrically connected to the first via plugs, in the first interlayer insulating film;

(d) forming a second resistor on the first metal wiring; and

(e) forming a second interlayer insulating film on the semiconductor substrate in which the second resistor is formed, and then forming a plurality of second via plugs that are electrically connected to the first metal wiring and the second resistor, and a second metal wiring that is electrically connected to the second via plug.

2. The method as claimed in claim 1 , wherein the first and second resistors are electrically connected in a serial manner.

3. The method as claimed in claim 1 , wherein the metal film is an aluminum film, the barrier film is a titanium nitride film, the dielectric film is a silicon nitride film, the conductive material film is a tantalum nitride film, and the etch-stop layer is a silicon nitride film.

4. The method as claimed in claim 1 , wherein the second resistor has a structure in which an insulating film, a conductive material film and an etch-stop layer are sequentially stacked.

Assignments (6)
CHANGE OF NAME Recorded Mar 12, 2024
From: KEY FOUNDRY CO., LTD.
To: SK KEYFOUNDRY INC.
Reel/Frame 066794/0290 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2020
From: MAGNACHIP SEMICONDUCTOR, LTD.
To: KEY FOUNDRY CO., LTD.
Reel/Frame 053703/0227 →
CORRECTIVE ASSIGNMENT TO CORRECT THE RECEIVING PARTY ADDRESS PREVIOUSLY RECORDED AT REEL: 024563 FRAME: 0807. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE BY SECURED PARTY. Recorded Nov 25, 2014
From: US BANK NATIONAL ASSOCIATION
To: MAGNACHIP SEMICONDUCTOR LTD.
Reel/Frame 034469/0001 →
RELEASE OF SECURITY INTEREST Recorded Jun 22, 2010
From: U.S. BANK NATIONAL ASSOCIATION
To: MAGNACHIP SEMICONDUCTOR LTD.
Reel/Frame 024563/0807 →
AFTER-ACQUIRED INTELLECTUAL PROPERTY KUN-PLEDGE AGREEMENT Recorded Feb 18, 2009
From: MAGNACHIP SEMICONDUCTOR, LTD.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL TRUSTEE
Reel/Frame 022277/0133 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 5, 2005
From: KEUM, SO HYEN; SHIN, SOO CHAN
To: MAGNACHIP SEMICONDUCTOR, LTD.
Reel/Frame 016746/0978 →