Lead frame and semiconductor device having the lead frame
Provided is a lead frame having an improved wire bonding property of inner leads and an improved soldering property of outer leads and preventing defects with high producing yield, and a method of manufacturing the lead frame. The lead frame includes a plurality of inner leads formed with predetermined intervals between them; and a plurality of outer leads extended from the inner leads in length directions of the inner leads, each of which has an end portion overlapped with the inner lead and coupled thereto and the other end connected to neighboring outer lead by a supporting portion.
1. A lead frame for a semiconductor device comprising:
a plurality of inner leads formed from a first lead frame and arranged in an inward direction of the lead frame with predetermined intervals between them; and
a plurality of outer leads formed from a second lead frame, the second lead frame having separate existence from the first lead frame, each of the outer leads arranged in a manner extending outwardly from a corresponding one of the inner leads, each of the outer leads having an inner end overlapped and connected with the corresponding one of the inner leads and an outer end connected to a supporting portion disposed at an outer area of the outer leads.
2. The lead frame of claim 1 , further comprising a dam bar formed along the outer leads in a transverse direction thereof and connecting the outer leads to one another.
3. The lead frame of claim 1 , further comprising a die pad disposed at an inward location from the inner leads.
4. The lead frame of claim 1 , wherein the inner leads including a first plating layer formed on an inner surface of the inner leads, the first plating layer containing at least one material selected from a group consisting of Ag, Au and Pd.
5. The lead frame of claim 4 , wherein the outer leads including a second plating layer formed thereon, the second plating layer containing Sn as a main material.
6. The lead frame of claim 1 , wherein the overlapped portions of the inner leads and the outer leads are connected together by welding or bonding.
7. A semiconductor device comprising:
a lead frame, the lead frame including a plurality of inner leads formed from a first lead frame and arranged in an inward direction of the lead frame, and a plurality of outer leads formed from a second lead frame, the second lead frame having separate existence from the first lead frame, each of the outer leads arranged in a manner extending outwardly from a corresponding one of the inner leads, each of the outer leads having one end portion overlapped and connected with the corresponding one of the inner leads;
a semiconductor chip disposed adjacent to a central location of the lead frame in a manner supported by the lead frame; and
an encapsulation material covering at least some portions of the semiconductor chip and the lead frame including the overlapped portion of the inner and outer leads.
8. The semiconductor device of claim 7 , wherein at least some portion of the inner leads of the lead frame is plated with a material enhancing wire-bonding capacity, and at least some portion of the outer leads of the lead frame is plated with a material enhancing solder-wettability.
9. The semiconductor device of claim 8 , wherein the material plated on the inner leads of the lead frame is a material containing at least one of Au, Ag and Pd.
10. The semiconductor device of claim 8 , wherein the material plated on the outer leads of the lead frame is a material containing Sn.
11. The semiconductor device of claim 7 , wherein the lead frame further includes a die pad disposed adjacent to a central location of the lead frame, and the semiconductor chip is positioned on the die pad.
12. The semiconductor device of claim 11 , wherein the lead frame further includes tie-bars for securing the die pad to the lead frame.
13. The semiconductor device of claim 7 , wherein the semiconductor chip is attached to the lower surface of the inner leads.
14. The semiconductor device of claim 13 , wherein the semiconductor chip is attached to the lower surface of the inner leads with conductive bumps disposed there-between.