Method and pixel for performing correlated double sampling
View Patent ↗A method and apparatus for performing correlated double sampling to remove low frequency noise. The method and apparatus includes an active pixel of an array of active pixels comprising a sensor circuit for collecting radiation induced charges and transducing them to a measurement signal corresponding to the amount of charge collected, two memory elements for storing the measurement signal at the beginning and the end of a first integration period respectively, and at least one further memory element for storing at least the measurement signal at the beginning of a next integration period.
1. An active pixel comprising:
a first sensor circuit configured to collect radiation induced charges and to transduce the radiation induced charges to a measurement signal corresponding to an amount of charge collected during an integration period of the first sensor circuit;
a first memory element configured to store a first measurement signal at a beginning of a first integration period of the first sensor circuit;
a second memory element configured to store a second measurement signal at an end of the first integration period of the first sensor circuit; and
a third memory element configured to store a third measurement signal at a beginning of a second integration period of the first sensor circuit, wherein the second integration period is an integration period of the first sensor circuit immediately subsequent to the first integration period.
2. An active pixel according to claim 1 , wherein the memory elements are capacitors.
3. An active pixel according to claim 1 , wherein the memory elements are parts of sample and hold stages.
4. An active pixel according to claim 1 , the memory elements having a first node, the active pixel furthermore comprising a pre-charge circuit to pre-charge the voltage on the first node of the memory elements.
5. An active pixel according to claim 1 , furthermore comprising a readout circuit connected to the memory elements, for reading out the measurement signal present on the node of a memory element.
6. An active pixel according to claim 5 , wherein a first buffer is provided between the memory elements and the readout circuit.
7. An active pixel according to claim 1 , wherein a second buffer is provided between the sensor circuit and the memory elements.
8. An active pixel according to claim 1 , wherein the sensor circuit comprises a series connection of a reverse-biased photodiode and a reset switch.
9. A method for performing correlated double sampling in an active pixel, comprising:
during at least a first and a second subsequent integration period of the active pixel, collecting radiation induced charges and transducing the radiation induced charges to a measurement signal;
storing, in a first memory element, a reset level of the pixel at a beginning of the first integration period of the active pixel;
storing, in a second memory element, a measurement signal of the pixel at an end of the first integration period of the active pixel; and
while performing the correlated double sampling with the stored reset level and the stored measurement signal, storing, in a third memory element, a reset level of the pixel at a beginning of the second integration period of the active pixel, wherein the second integration period is an integration period of the active pixel immediately subsequent to the first integration period.
10. A method according to claim 9 , furthermore comprising a step of pre-charging a memory element before storing a signal.
11. A method according to claim 9 , the active pixel comprising a photodiode, the method furthermore comprising a step of resetting the photodiode to a preset voltage level before the beginning of an integration period.
12. An array of active pixels, each active pixel comprising:
a first sensor circuit configured to collect radiation induced charges and to transducer the radiation induced charges to a measurement signal corresponding to an amount of charge collected during an integration period of the first sensor circuit;
a first memory element configured to store a first measurement signal at a beginning of a first integration period of the first sensor circuit;
a second memory element configured to store a second measurement signal at an end of the first integration period of the first sensor circuit; and
a third memory element configured to store a third measurement signal at a beginning of a second integration period of the first sensor circuit, wherein the second integration period is an integration period of the first sensor circuit immediately subsequent to the first integration period.
13. An array of active pixels according to claim 12 , wherein the memory elements are capacitors.
14. An array of active pixels according to claim 12 , wherein the memory elements are parts of sample and hold stages.
15. An array of active pixels according to claim 12 , the memory elements having a first node, wherein each active pixel furthermore comprises a pre-charge circuit to pre-charge the voltage on the first node of the memory elements.
16. An array of active pixels according to claim 12 , further comprising a readout circuit connected to the memory elements, for reading out the signals stored on the memory elements.
17. An array of active pixels according to claim 16 , wherein in each pixel a first buffer is provided between the memory elements and the readout circuit.
18. An array of active pixels according to claim 12 , wherein in each pixel a second buffer is provided between the sensor circuit and the memory elements.
19. An array of active pixels according to claim 12 , wherein the sensor circuit of each pixel comprises a series connection of a reverse biased photodiode and a reset switch.
20. An array of active pixels according to claim 12 , further comprising a circuit for controlling the timing of pre-charging of all the active pixels of the array at the same time.