Read-only memory array with dielectric breakdown programmability
According to one exemplary embodiment, a programmable ROM array includes at least one bitline situated in a substrate. The programmable ROM array further includes at least one wordline situated over the at least one bitline. The programmable ROM array further includes a memory cell situated at an intersection of the at least one bitline and the at least one wordline, where the memory cell includes a dielectric region situated between the at least one bitline and the at least one wordline. A programming operation causes the memory cell to change from a first logic state to a second logic state by causing the dielectric region to break down. The programming operation causes the memory cell to operate as a diode. A resistance of the memory cell can be measured in a read operation to determine if the memory cell has the first or second logic state.
1 . A programmable ROM array comprising:
at least one bitline situated in a substrate;
at least one wordline situated over said at least one bitline;
a memory cell situated at an intersection of said at least one bitline and said at least one wordline, said memory cell comprising a dielectric region situated between said at least one bitline and said at least one wordline;
wherein a programming operation causes said memory cell to change from a first logic state to a second logic state by causing said dielectric region to break down.
2 . The programmable ROM array of claim 1 wherein a difference between a first voltage applied to said at least one wordline and a second voltage applied to said at least one bitline during said programming operation causes said dielectric region to break down.
3 . The programmable ROM array of claim 1 wherein said programming operation causes said memory cell to operate as a diode.
4 . The programmable ROM array of claim 1 wherein said at least one wordline comprises an N type semiconductor.
5 . The programmable ROM array of claim 4 wherein said N type semiconductor has an N type dopant concentration of between approximately 1.0×10 18 cm −3 and approximately 1.0×10 20 cm −3 .
6 . The programmable ROM array of claim 1 wherein said at least one bitline comprises a P type semiconductor.
7 . The programmable ROM array of claim 1 wherein said dielectric region has a thickness of between approximately 50.0 Angstroms and approximately 200.0 Angstroms.
8 . The programmable ROM array of claim 1 wherein a resistance of said memory cell is measured in a read operation to determine if said memory cell has said first logic state or said second logic state.
9 . The programmable ROM array of claim 1 wherein said dielectric region comprises a single layer of dielectric material, wherein said dielectric material is selected from the group consisting of silicon oxide, aluminum oxide, hafnium oxide, silicon nitride, zirconium oxide, and titanium oxide.
10 . The programmable ROM array of claim 1 wherein said dielectric region comprises an ONO stack.
11 . A programmable ROM array comprising:
at least one bitline situated in a substrate, said at least one bitline comprising a P type semiconductor;
at least one wordline situated over said at least one bitline, said at least one wordline comprising an N type semiconductor;
a memory cell situated at an intersection of said at least one bitline and said at least one wordline, said memory cell comprising a dielectric region situated between said at least one bitline and said at least one wordline;
wherein a programming operation causes said memory cell to change from a first logic state to a second logic state by causing said dielectric region to break down, and wherein said programming operation causes said memory cell to operate as a diode.
12 . The programmable ROM array of claim 11 wherein a difference between a first voltage applied to said at least one wordline and a second voltage applied to said at least one bitline during said programming operation causes said dielectric region to break down.
13 . The programmable ROM array of claim 11 wherein said N type semiconductor has an N type dopant concentration of between approximately 1.0×10 18 cm −3 and approximately 1.0×10 20 cm −3 .
14 . The programmable ROM array of claim 11 wherein said dielectric region has a thickness of between approximately 50.0 Angstroms and approximately 200.0 Angstroms.
15 . The programmable ROM array of claim 11 wherein a resistance of said memory cell is measured in a read operation to determine if said memory cell comprises said first logic state or said second logic state.
16 . The programmable ROM array of claim 11 wherein said dielectric region comprises a single layer of dielectric material.
17 . The programmable ROM array of claim 16 wherein said dielectric material is selected from the group consisting of silicon oxide, aluminum oxide, hafnium oxide, silicon nitride, zirconium oxide, and titanium oxide.
18 . The programmable ROM array of claim 11 wherein said dielectric region comprises an ONO stack.
19 . The programmable ROM array of claim 11 wherein a resistance of said memory cell is greater than 10.0 Kilo Ohms in said first logic state.
20 . The programmable ROM array of claim 11 wherein said memory cell has a forward bias resistance of less than 10.0 Ohms in said second logic state.