Method for manufacturing NAND flash device

1. A method for manufacturing a NAND flash device comprising

providing a semiconductor substrate on which a drain select transistor is formed for selecting a drain terminal of a flash cell and a source select transistor is formed for selecting a source terminal of the flash cell, wherein the drain select transistor and the source select transistor have drain region and a source region on the surface of the semiconductor substrate;

forming a first interlayer insulating film over the semiconductor substrate;

removing a portion of the first interlayer insulating film to form a source line contact hole, wherein the source region of the source select transistor is exposed at the bottom of the source line contact hole;

removing a portion of the first interlayer insulating film to form a drain contact hole, wherein the drain region of the drain select transistor is exposed at the bottom of the drain contact hole;

forming a source line plug and a drain contact plug in the source line contact hole and the drain contact hole, respectively;

forming a bit line connected to the drain contact plug and a common source line contact connected to the source line plug;

forming at least of one insulating film over the semiconductor substrate including the source line plug and the drain contact plug;

selectively etching the insulating film and forming a first trench and a second trench in the insulating film, wherein the first trench is formed over the drain contact plug and the second trench is formed over the source line plug;

selectively etching the insulating film and forming a first via hole and a second via hole under the first trench and second trench respectively, wherein the first via hole exposes the drain contact plug and the second via hole exposes the source line plug;

filling the first trench, the second trench, the first via hole and the second via hole with a metal film; and,

forming a bit line passing the first trench and the first via hole and a common source line contact passing the second trench and the second via hole by polishing the metal film.

2. The method of claim 1 , wherein the first trench is larger than the second trench.

3. The method of claim 1 , wherein forming the insulating film comprises:

forming a second interlayer insulating film over the semiconductor substrate including the source line plug and the drain contact plug;

forming an etch-stop layer on the second interlayer insulating layer; and,

forming a third interlayer insulating film on etch-stop layer.

4. The method of claim 3 , comprising forming the first and the second trenches by selectively etching the third interlayer insulating film, the etch-stop layers, and portions of the second interlayer insulating layer.

5. The method of claim 4 , comprising forming the first via hole and the second via hole in the second interlayer insulating layer.

6. The method of claim 1 , further comprising the step of implanting impurities into the source region and the drain region which are exposed at the bottoms of the source line contact hole and the drain contact hole respectively.

7. The method of claim 6 , wherein the forming of the source line plug and the drain contact plug comprises:

forming a conductive film over an entire structure including the source line contact hole and the drain contact hole; and,

performing a chemical mechanical polishing process to the conductive layer with the first interlayer insulating film as a stop layer.

8. The method of claim 7 , wherein the conductive layer is a polysilicon layer.