Process for fabricating an integrated circuit package
View Patent ↗A process for fabricating an integrated circuit package. At least a first side of a leadframe strip is selectively etched to define portions of a die attach pad and at least one row of contacts adjacent the die attach pad. A carrier strip is laminated to the first side of the leadframe strip and a second side of the leadframe strip is selectively etched to thereby define a remainder of the die attach pad and the at least one row of contacts. A semiconductor die is mounted to the die attach pad, on the second side of the leadframe strip and the semiconductor die is wire bonded to ones of the contacts. The second side of the leadframe strip is encapsulating, including the semiconductor die and wire bonds, in a molding material. The carrier strip is removed from the leadframe strip and the integrated circuit package is singulated from a remainder of the leadframe strip.
1. A process for fabricating an integrated circuit package, comprising:
selectively etching at least a first side of a leadframe strip to define portions of a die attach pad and at least one row of contacts adjacent said die attach pad;
laminating a carrier strip to said first side of said leadframe strip;
selectively etching a second side of said leadframe strip to thereby define a remainder of said die attach pad and said at least one row of contacts;
mounting a semiconductor die to said die attach pad, on the second side of the leadframe strip;
wire bonding said semiconductor die to ones of said contacts;
encapsulating said second side of said leadframe strip, including said semiconductor die and wire bonds, in a molding material;
removing said carrier strip from said leadframe strip; and
singulating said integrated circuit package from a remainder of said leadframe strip.
2. The process for fabricating the integrated circuit package according to claim 1 , further comprising:
plating said carrier strip for facilitating lamination, prior to laminating said carrier strip to said first side of said leadframe strip.
3. The process for fabricating the integrated circuit package according to claim 2 , wherein said plating comprises plating metal on both sides of said carrier strip for facilitating lamination.
4. The process for fabricating the integrated circuit package according to claim 2 , wherein said plating comprises plating one of Tin (Sn), Solder, Palladium (Pd), Silver (Ag) and layers of Nickel and Gold (Ni/Au) on said leadframe strip.
5. The process for fabricating the integrated circuit package according to claim 3 , wherein said metal that is plated on both sides of said carrier strip, acts as an etch resistant layer.
6. The process for fabricating the integrated circuit package according to claim 1 , wherein said selectively etching said second side of said leadframe strip comprises:
selectively plating an etch-resistant metal on said second side of said leadframe strip; and
etching said leadframe strip to thereby define said remainder of said die attach pad and said at least one row of contacts.
7. The process for fabricating the integrated circuit package according to claim 1 , wherein said selectively etching said first side of said leadframe strip comprises:
depositing a photo-imageable etch-resistant mask on said first side of said leadframe strip;
imaging and developing said mask to expose portions of said first side of said leadframe strip; and
etching said first side of said leadframe strip to thereby etch said exposed portions of said first side of said leadframe strip.
8. The process for fabricating the integrated circuit package according to claim 1 , wherein said laminating said carrier strip to said first side of said leadframe strip comprises laminating at elevated temperature and pressure.
9. The process for fabricating the integrated circuit package according to claim 1 , wherein said laminating said carrier strip to said first side of said leadframe strip comprises laminating using solder reflow technique.
10. The process for fabricating the integrated circuit package according to claim 1 , wherein said removing said carrier strip comprises:
heating the laminated strip and pulling said carrier strip from said leadframe strip.
11. The process for fabricating the integrated circuit package according to claim 1 , further comprising:
mounting a plurality of contact balls on said first side of said leadframe strip, in the form of a ball grid array, ones of said contact balls being electrically connected to ones of said contacts, after removing said carrier strip and prior to singulating.
12. The process for fabricating the integrated circuit package according to claim 1 , further comprising solder reflowing after removing the carrier strip.
13. The process for fabricating the integrated circuit package according to claim 1 , wherein the carrier strip is a metal strip.
14. The process for fabricating the integrated circuit package according to claim 1 , further comprising gang testing individual units of the leadframe strip prior to singulating said integrated circuit package.